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1 zarlink semiconductor inc. zarlink, zl and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2003, zarlink semiconductor inc. all rights reserved. features ? 4 gigabit ports with gmii and pcs interface - gigabit port can also support 100/10 mbps mii interface ? high performance layer 2 packet forwarding (11.904m packets per second) and filtering at full-wire speed ? maximum throughput is 4 gbps non-blocking ? centralized shared-memory architecture ? consists of two memory domains at 133 mhz - frame buffer domain: one bank of zbt-sram with 1m/2mb total - switch database domain with 256k/512k sram. ? up to 64k mac addresses to provide large node aggregation in wiring closet switches traffic classification ? classify traffic into 8 transmission priorities per port ? supports delay bounded, strict priority, and wfq ? provides 2 level dropping precedence with wred mechanism - user controlled thresholds for wred ? classification based on layer 2, 3 markings - vlan priority field in vlan tagged frame. - ds/tos field in ip packet - the precedence of above two classifications can be programmable ? qos support ? supports ieee 802.1p/q quality of service with 8 priority ? buffer management: reserve buffers on per class and per port basis october 2003 ordering information MVTX2801ag 596-pin hsbga -40 c to +85 c MVTX2801 unmanaged 4-port 1000 mbps ethernet switch data sheet figure 1 - chip block diagram vtx2800 gmii /pcs port 0 gmii /pcs port 1 gmii /pcs port 2 gmii /pcs port 3 management module frame engine search engine frame data buffer a zbt-sram (1m/2mb) 64bit serial / i2c scheduler sdb interface fdb interface sw databasee 32bit sram 256/512k mac table nm database led
MVTX2801 data sheet 2 zarlink semiconductor inc. ? port-based priority: vlan priority with tagged fr ame can be overwritten by the priority of pvid ? qos features can be configured on a per port basis control ? full duplex ethernet ieee 802.3x flow control ? provides ethernet multicast and broadcast control ? 2 port trunking groups, max of 3 ports per group (t runking can be based on source mac and/or destination mac and source port) ? led signals provided by a se rial or parallel interface ? synchronous serial interface and i 2 c interface in unmanaged mode. ? hardware auto-negotiation through serial management in terface (mdio) for gigabit ethernet ports, supports 10/100/1000 mbps ? bist for internal and external sram-zbt ?i 2 c eeprom or synchronous serial port for configuration ? packaged in 596-pin bga description the mvtx2800 family is a group of 1000 mbps non-blocki ng ethernet switch chips with on-chip address memory. a single chip provides a maximum of eight 1000 mbps ports and a dedicated cpu interf ace with a 16/8-bit bus for managed and unmanaged switch applications. the mvtx28 00 family consists of the following four products: ? mvtx2804 8 gigabit ports managed ? mvtx2803 8 gigabit ports unmanaged ? mvtx2802 4 gigabit ports managed ? MVTX2801 4 gigabit ports unmanaged the MVTX2801 supports up to 64k mac addresses to aggregate traffic from multiple wiring closet stacks. the centralized shared-memory architecture allows a very hi gh performance packet-forwarding rate of 11.904m packet per second at full wire speed. the chip is optimized to provide a low-cost, high performance workgroup, and wiring closet, layer 2 switching solution with 4 gigabit ethernet ports. one frame buffer memory do main utilize cost effective, high-perfo rmance zbt-sram with aggregated bandwidth of 8.5gbps to support full wire speed on all external ports simultaneously. with strict priority, delay bounded, and wrr transmis sion scheduling, plus wred memory congestion scheme, the chip provides powerful qos functions for convergent network multimedia and mission-critical applications. the chip provides 8 transmission priorities and 2 level drop pr ecedence. traffic is assigned its transmission priority and dropping precedence based on the frame vlan tag priority. the MVTX2801 supports port trunking/load shar ing on the 1000 mbps ports with fail-over capability. the port trunking/load sharing can be used to group ports between interlinked switches to increase the effective network bandwidth. in full-duplex mode, ieee 802.3x flow control is provided. the physical codi ng sublayer (pcs) is integrated on- chip to provide a direct 10-bit gmii interface, or the pcs can be bypassed to provide an interface to existing fiber- based gigabit ethernet transceivers. the MVTX2801 is fabricated using 0.25( m technology. inputs, however, are 3.3v tolerant and the outputs are capable of directly interfacing to lvttl levels. the mv tx2801 is packaged in a 596-pin ball grid array package.
MVTX2801 data sheet table of contents 3 zarlink semiconductor inc. 1.0 block functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.1 frame data buffer (fdb) interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.2 switch database (sdb) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 gmii/pcs mac module (gmac) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.4 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.5 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.6 led interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.7 internal memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.0 system configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1 i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.1 start condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.2 address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.3 data direction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.4 acknowledgment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.5 data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.6 stop condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2 synchronous serial interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.1 write command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.2.2 read command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.0 data forwarding protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.1 unicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 multicast data frame forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.0 memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 4.2 detailed memory information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.0 search engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.1 search engine overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 basic flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3 search, learning, and aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.1 mac search. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.3.2 learning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.3 aging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.3.4 data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.0 frame engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.1 data forwarding summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2 frame engine details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2.1 fcb manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.2.2 rx interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.3 rxdma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2.4 txq manager . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 port control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.4 txdma. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.0 quality of service and flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.1 model. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.2 four qos configurations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.3 delay bound . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.4 strict priority and best effort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.5 weighted fair queuing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.6 shaper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.7 wred drop threshold management support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.8 buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
MVTX2801 data sheet 4 zarlink semiconductor inc. 7.8.1 dropping when buffers are scarce . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.9 flow control basics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7.9.1 unicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.9.2 multicast flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 7.10 mapping to ietf diffserv classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8.0 port trunking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.1 features and restrictions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.2 unicast packet forwarding. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 8.3 multicast packet forwarding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 8.4 preventing multicast packets from looping back to the source trunk. . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.0 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.2 serial mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9.3 parallel mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 9.4 led control registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10.0 register definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.1 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 10.2 group 0 address - mac ports group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.1 ecr1pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 10.2.2 ecr2pn: port n control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 10.2.3 ggcontrol 0- extra giga port cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.2.4 ggcontrol 1- extra giga port cont rol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 10.3 group 1 address - vlan group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.3.1 avtcl - vlan type code register low . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 10.3.2 avtch - vlan type code register hig h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 10.3.3 pvmap00_0 - port 00 configuration register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 10.3.4 p pvmap00_3 - port 00 configuration register 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 10.3.5 pvmode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.4 group 2 address - port trunking grou p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.4.1 trunk0_mode - trunk group 0 and 1 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 10.4.2 tx_age - tx queue aging timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5 group 4 address - search engine group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5.1 agetime_low - mac addre ss aging time low. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5.2 agetime_high -mac address aging ti me high . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 10.5.3 se_opmode - search engine operatio n mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.6 group 5 address - buffer control/qos group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.6.1 fcbat - fcb aging timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.6.2 qosc - qos control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10.6.3 fcr - flooding control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.6.4 avpml - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 10.6.5 avpmm - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.6.6 avpmh - vlan priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.6.7 tospml - tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10.6.9 tospmh - tos priority map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.6.10 avdm - vlan discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 10.6.11 tosdml - tos discard map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.6.12 bmrc - broadcast/multicast rate cont rol. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 10.6.13 ucc - unicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.6.14 mcc - multicast congestion control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.6.15 prg - port reservation for giga po rts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 10.6.16 sfcb - share fcb size. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.6.17 c2rs - class 2 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 10.6.18 c3rs - class 3 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.6.19 c4rs - class 4 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
MVTX2801 data sheet 5 zarlink semiconductor inc. 10.6.20 c5rs - class 5 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.6.21 c6rs - class 6 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 10.6.22 c7rs - class 7 reserved size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6.23 qosc00 - byte_c2_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6.24 qosc01 - byte_c3_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6.25 qosc02 - byte_c4_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6.26 qosc03 - byte_c5_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 10.6.27 qosc04 - byte_c6_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.28 qosc05 - byte_c7_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.29 qosc06 - byte_c2_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.30 qosc07 - byte_c3_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.31 qosc08 - byte_c4_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.32 qosc09 - byte_c5_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10.6.33 qosc0a - byte_c6_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6.34 qosc0b - byte_c7_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6.35 qosc0c - byte_c2_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6.36 qosc0d - byte_c3_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6.37 qosc0e - byte_c4_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 10.6.38 qosc0f - byte_c5_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6.39 qosc10 - byte_c6_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6.40 qosc11 - byte_c7_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6.41 qosc12 - byte_c2_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6.42 qosc13 - byte_c3_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 10.6.44 qosc15 - byte_c5_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6.45 qosc16 - byte_c6_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6.46 qosc17 - byte_c7_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6.47 qosc33 - credit_c0_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 10.6.48 qosc34 - credit_c1_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.6.49 qosc35 - credit_c2_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.6.50 qosc36 - credit_c3_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.6.51 qosc37 - credit_c4_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 10.6.52 qosc38 - credit_c5_g0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.6.53 qosc39- credit_c6_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.6.54 qosc3a- credit_c7_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.6.55 qosc3b - credit_c0_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 10.6.56 qosc3c - credit_c1_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6.57 qosc3d - credit_c2_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6.58 qosc3e - credit_c3_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6.59 qosc3f - credit_c4_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 10.6.60 qosc40 - credit_c5_g1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6.61 qosc41- credit_c6_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6.62 qosc42- credit_c7_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6.63 qosc43 - credit_c0_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 10.6.64 qosc44 - credit_c1_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6.65 qosc45 - credit_c2_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6.66 qosc46 - credit_c3_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6.67 qosc47 - credit_c4_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10.6.68 qosc48 - credit_c5_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.6.69 qosc49- credit_c6_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.6.70 qosc4a- credit_c7_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.6.71 qosc4b - credit_c0_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 10.6.72 qosc4 - credit_c1_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.6.73 qosc4d - credit_c2_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.6.74 qosc4e - credit_c3_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
MVTX2801 data sheet 6 zarlink semiconductor inc. 10.6.75 qosc4f - credit_c4_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 10.6.76 qosc50 - credit_c5_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.77 qosc51- credit_c6_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.78 qosc52- credit_c7_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.79 qosc73 - token_rate_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.80 qosc74 - token_limit_g0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.6.81 qosc75 - token_rate_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.82 qosc76 - token_limit_g1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.83 qosc77 - token_rate_g2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.84 qosc78 - token_limit_g2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.85 qosc79 - token_rate_g3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.6.86 qosc7a - token_limit_g3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.6.87 rdrc0 - wred rate control 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.6.88 rdrc1 - wred rate control 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.7 group 6 address - misc group . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.7.1 mii_op0 - mii regi ster option 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.7.2 mii_op1 - mii regi ster option 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.7.3 fen - feature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.7.4 miic0 - mii command register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.7.5 miic1 - mii command register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.7.6 miic2 - mii command register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 10.7.7 miic3 - mii command register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.7.8 miid0 - mii data regist er 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.7.9 miid1 - mii data register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.7.10 led mode - led control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.7.11 checksum - eeprom ch ecksum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 10.7.12 led user . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.7.13 leduser0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.7.14 leduser1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.7.15 leduser2/ledsig2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 10.7.16 leduser3/ledsig3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.7.17 leduser4/ledsig4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 10.7.18 leduser5/ledsig5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.7.19 leduser6/ledsig6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 10.7.20 leduser7/ledsig1_0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 10.7.21 miinp0 - mii next page data register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.7.22 miinp1 - mii next page data register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.8 group f address - cpu access group. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.8.1 gcr-global control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.8.2 dcr-device status and signature register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 10.8.3 dcr01-giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.8.4 dcr23-giga port status. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.8.5 dpst - device port status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.8.6 dtst - data read back register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 11.0 bga and ball signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.1 bga views (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 11.2 ball- signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 11.3 ball signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 11.4 characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.4.2 dc electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 11.4.3 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 11.5 ac characteristics and timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 11.5.1 typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
MVTX2801 data sheet 7 zarlink semiconductor inc. 11.5.2 local frame buffer zbt sram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.5.2.1 local zbt sram memory interface a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 11.5.3 local switch database sbram memory in terface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.3.1 local sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 11.5.4 media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 11.5.5 gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 11.5.6 pcs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 11.5.7 led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 11.5.8 mdio input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 11.5.9 i 2 c input setup timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 11.5.10 serial interface setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MVTX2801 data sheet list of figures 8 zarlink semiconductor inc. figure 1 - chip block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2 - data transfer format for i 2 c interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 3 - sram interface block diagram (dmas for gigabit ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 4 - buffer partition scheme used in the MVTX2801. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 5 - bga diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 figure 6 - typical reset & bootstrap timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 figure 7 - local memory interface - input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 8 - local memory interface - output valid delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 9 - local memory interface - input setup and hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 10 - local memory interface - output valid delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 11 - ac characteristics - media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 12 - ac characteristics - media in dependent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 13 - ac characteristics- gmii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 14 - ac characteristics - gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 15 - ac characteristics - pcs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 16 - ac characteristics - pcs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 17 - ac characteristics - led inte rface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 18 - mdio input setup and hold timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 19 - mdio output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 20 - i 2 c input setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 21 - i 2 c output delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 22 - serial interface setup timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 23 - serial interface output delay timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MVTX2801 data sheet list of tables 9 zarlink semiconductor inc. table 1 - two-dimensional world traffic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 table 2 - four qos configurations per port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 3 - wred dropping scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 4 - mapping between MVTX2801 and ietf diffserv classes for gigabit ports . . . . . . . . . . . . . . . . . . . . . . 23 table 5 - MVTX2801 features enabling ietf diffserv standards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 table 6 - timing diagram for serial mode in led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 7 - MVTX2801 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 8 - ball- signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 table 9 - ball signal name. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 table 10 - recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 11 - reset & bootstrap timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 table 12 - ac characteristics - local frame buffer zbt-sram memo ry interface a. . . . . . . . . . . . . . . . . . . . . . . 96 table 13 - ac characteristics - local swit ch database sbram memory interface . . . . . . . . . . . . . . . . . . . . . . . 97 table 14 - ac characteristics - media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 table 15 - ac characteristics - gigabit media independent interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 table 16 - ac characteristics - pcs interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 table 17 - ac characteristics - led interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 table 18 - mdio timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 table 19 - i 2 c timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 table 20 - serial interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
MVTX2801 data sheet 10 zarlink semiconductor inc. 1.0 block functionality 1.1 frame data buffer (fdb) interfaces the fdb interface supports pipelined zbt-sram memory at 133 mhz. to ensure a non-blocking switch, one memory domain is required. each domain has a 64-bi t wide memory bus. at 133 mhz, the aggregate memory bandwidth is 8.5 gbps, which is enough to support 4 gig abit ports at full wire speed switching. a patent pending scheme is used to access the fdb memory. each slot has one tick to read or write 8 bytes. 1.2 switch database (sdb) interface a pipelined synchronous burst sram (sbram) memory is us ed to store the switch dat abase information including mac table. search engine accesses the switch database via sdb interface. the sdb bus has 32-bit wide bus at 133mhz. 1.3 gmii/pcs mac module (gmac) the gmii/pcs media access control (mac) module provid es the necessary buffers and control interface between the frame engine (fe) and the external physical device (phy). the MVTX2801 has two interfaces, gmii or pcs. the mac of the MVTX2801 meets the ieee 802.3z specific ation and supports the mii inte rface. it is abl e to operate 10m/100m/1g in full duplex mode with a back pressure/flow control mechanism. it has the options to insert source address/crc/vlan id to each frame. the gmi i/pcs module also supports hot plug detection. 1.4 frame engine the main function of the frame engine is to forward a frame to its proper destination port or ports. when a frame arrives, the frame engine parses the frame header (64 bytes) and formulates a switching request, which is sent to the search engine to resolve the destination port. the arriving frame is moved to the fdb. after receiving a switch response from the search engine, the frame engine perfor ms transmission scheduling based on the frame's priority. the frame engine forwards the frame to the mac module when the frame is ready to be sent. 1.5 search engine the search engine resolves the frame's destination port or ports according to the destination mac address (l2) by searching the database. it also performs mac learning, priority assignment, and trunking functions. 1.6 led interface the led interface can be operated in a serial mode or a parallel mode. in the serial mode, the led interface uses 3 pins for carrying 4 port status signals . in the parallel mode, the interface can drive leds by 8 status pins. the led port is shared with bootstrap pins. in order to avoid er ror when reading the bootstraps, a buffer must be used to isolate the led circuitry from the bootstrap pins during boo tstrap cycle (the bootstrap pins are sampled at the rising edge of the reset). 1.7 internal memory several internal tables are required and are described as follows: ? frame control block (fcb) - each fcb entry contains the control information of the associated frame stored in the fdb, e.g. frame size, read/writ e pointer, transmission priority, etc. ? mct link table - the mct link table stores the linked li st of mct entries that have collisions in the external mac table.
MVTX2801 data sheet 11 zarlink semiconductor inc. 2.0 system configuration the MVTX2801 can be configured by eeprom (24c02 or compatible) via an i 2 c interface at boot time, or via a synchronous serial interface during operation. 2.1 i 2 c interface the i 2 c interface uses two bus lines, a serial data line (sda) and a serial clock line (scl). the scl line carries the control signals that fac ilitate the transfer of information from eeprom to the switch. data tran sfer is 8-bit serial and bi-directional, at 50 kbps. data transfer is perf ormed between master and slave ic using a request / acknowledgment style of protocol. the master ic generates the timing signals and terminates data transfer. the figure below shows the data transfer format. figure 2 - data transfer format for i 2 c interface 2.1.1 start condition generated by the master, the MVTX2801. the bus is consid ered to be busy after the start condition is generated. the start condition occurs if while the scl line is high, there is a hi gh-to-low transition of the sda line. other than in the start condition (and stop condition), th e data on the sda line must be st able during the high period of scl. the high or low state of sda can only change when scl is low. in addition, when the i 2 c bus is free, both lines are high. 2.1.2 address the first byte after the start conditi on determines which slave the master will select. the slave in our case is the eeprom. the first seven bits of the firs t data byte make up the slave address. 2.1.3 data direction the eighth bit in the first byte after the start conditio n determines the direction (r/w ) of the message. a master transmitter sets this bit to w; a ma ster receiver sets this bit to r. 2.1.4 acknowledgment like all clock pulses, the master generates the acknowle dgment-related clock pulse. however, the transmitter releases the sda line (high) during the acknowledgment cl ock pulse. furthermore, the receiver must pull down the sda line during the acknowledge pulse so that it remains st able low during the high period of this clock pulse. an acknowledgment pulse follows every byte transfer. if a slave receiver does not acknowledge after any byte, th en the master generates a stop condition and aborts the transfer. if a master receiver does not acknowledge after any byte, then the slave transmitter must release the sda line to let the master generate the stop condition. 2.1.5 data after the first byte containi ng the address, all bytes that follow are data bytes. each byte must be followed by an acknowledge bit. data is transferred msb-first. start slave address r/w ack data 1 (8 bits) ack data 2 ack data m ack stop
MVTX2801 data sheet 12 zarlink semiconductor inc. 2.1.6 stop condition generated by the master. the bus is considered to be fr ee after the stop condition is generated. the stop condition occurs if while the scl line is high, there is a low-to-high transition of the sda line. the i 2 c interface serves the function of configuring the mv tx2801 at boot time. the ma ster is the MVTX2801, and the slave is the eeprom memory. 2.2 synchronous serial interface the synchronous serial interfac e serves the function of configuring the mv tx2801 not at boot time but via a pc. the pc serves as master and the MVTX2801 se rves as slave. the protocol for the synchronous serial interface is nearly identical to the i 2 c protocol. the main difference is that there is no acknowledgment bit after each byte of data transferred. the unmanaged MVTX2801 uses a synchronous serial interfac e to program the internal registers. to reduce the number of signals required, the register address, command and data are shifted in serially through the ps_di pin. ps_strobe pin is used as the shift clock. ps_do pin is used as data return path. each command consists of four parts. ? start pulse ? register address ? read or write command ? data to be written or read back any command can be aborted in the middle by sending an abort pulse to the MVTX2801. a start command is detected when ps_di is sampled high at ps_strobe - leading edge, and ps_di is sampled low when strobe- falls. an abort command is detected when ps_di is sampled lo w at ps_strobe - leading e dge, and ps_di is sampled high when ps_strobe - falls. 2.2.1 write command ps-strobe- ps_di a0 a2 ... a9 a10 a11 a1 w d0 d1 d2 d3 d4 d5 d6 d7 start address command data 2 extra clocks after last transfer
MVTX2801 data sheet 13 zarlink semiconductor inc. 2.2.2 read command all registers in the MVTX2801 can be modified through this synchronous serial interface. 3.0 data forwarding protocol 3.1 unicast data frame forwarding when a frame arrives, it is assigned a handle in memory by the frame control buffer manager (fcb manager). an fcb handle will always be available, beca use of advance bu ffer reservations. the memory (zbt-sram) interface is a 64-bit bus, conn ected to a zbt-sram domain. the receive dma (rxdma) is responsible for multiplexing the da ta and the address. on a port's ?turn,? the rx dma will move 8 bytes (or up to the end-of-frame) from the port's associated rxfi fo into memory (frame data buffer, or fdb). once an entire frame has been moved to the fdb, and a good end-of-frame (eof) has been received, the rx interface makes a switch request. the rxdma arbitrates among multiple switch requests. the switch request consists of the first 64 bytes of a frame, containing among other things, the source and destination mac addresses of the frame. the search engine places a switch response in the switch response queue of the frame engine when d one. among other inform ation, the search eng ine will have resolved the destination port of the frame and will have determi ned that the fr ame is unicast. after processing the switch response, the transmission queue manager (txq manager) of the frame engine is responsible for notifying the destination port that it has a frame to forward to it. but first, the txq manager has to decide whether or not to drop the frame, based on glob al fdb reservations and usage, as well as txq occupancy at the destination. if the frame is not dropped, then the txq manager links the frame's fcb to the correct per-port-per-class txq. unicast txq's ar e linked lists of transmissi on jobs, represented by their associated frames' fcb's. there is one linked list for each transmission class fo r each port. there are 8 classes for each of the 4 gigabit ports - a total of 32 unicast queues. the txq manager is responsible for scheduling transmissi on among the queues representing different classes for a port. when the port control module determines that th ere is room in the mac transmission fifo (txfifo) for another frame, it requests the handle of a new frame from the txq manager. the txq manager chooses among the head-of-line (hol) frames from the per-class queues fo r that port, using a zarlink semiconductor scheduling algorithm. ps_strobe- ps_di ps_do a0 a1 a2 ... a9 a10 a11 r d0 d1 d2 d3 d4 d5 d6 d7 start address command data
MVTX2801 data sheet 14 zarlink semiconductor inc. as at the transmit end, each of the 4 ports has time slots devoted solely to reading data from memory at the address calculated by port control. the transmission dma (txdma) is responsible for multiplexing the data and the address. on a port's turn, the txdma will move 8 by tes (or up to the eof) from memory into the port's associated txfifo. after reading the eof, the port control requests a fcb re lease for that frame. the txdma arbitrates among multiple buffer release requests. the frame is transmitted from the txfifo to the line. 3.2 multicast data frame forwarding after receiving the switch re sponse, the txq manager has to make the dropping decision. a global decision to drop can be made, based on global fdb utiliz ation and reservations. if so, then the fcb is released and the frame is dropped. in addition, a selective decision to drop can be made, based on the txq occupancy at some subset of the multicast packet's destinations. if so, then the frame is dr opped at some destinations but not others, and the fcb is not released. if the frame is not dropped at a particular de stination port, then the txq manager formats an entry in the multicast queue for that port and class. multicast qu eues are physical queues (unlike the linked lists for unicast frames). there are 4 multicast queues for each of the 4 gigabit ports. during scheduling, the txq manager treats the unicast q ueue and the multicast queue of the same class as one logical queue. the port control requests a fcb rele ase only after the eof for the multicast frame has been read by all ports to which the frame is destined. 4.0 memory interface 4.1 overview the figure below illustra tes the first part of the zbt- sram interface for the mvtx28 01. as shown, a 64 bit bus zbt-sram bank a is used for tx/rxdma access. becaus e the clock frequency is 133 mhz, the total memory bandwidth is 64-bits x 133 mhz = 8.5 gbps, for frame data buffer (fdb) access. figure 3 - sram interface block diagram (dmas for gigabit ports) tx dma 2-3 tx dma 0-1 rx dma 2-3 rx dma 0-1 zbt-sram bank a
MVTX2801 data sheet 15 zarlink semiconductor inc. 4.2 detailed memory information because the memory bus is 64 bits wide, frames are broken into 8-byte granules, written to and read from each memory access. in the worst case, a 1-byte-long eof granu le gets written to memory bank. this means that a 7-byte segment of memory bus is idle. the scenario re sults in a maximum 7 bytes of waste per frame, which is always acceptable because t he interfame gap is 20 bytes. 5.0 search engine 5.1 search engine overview the MVTX2801 search engine is optimized for high throu ghput searching, with enhanced features to support: ? up to 64k mac addresses ? 4 groups of port trunking ? traffic classification into 8 transmiss ion priorities, and 2 drop precedence levels 5.2 basic flow shortly after a frame enters the MVTX2801 and is writ ten to the frame data buffer (fdb), the frame engine generates a switch request, which is sent to the search e ngine. the switch request consis ts of the first 64 bytes of the frame, which contain all the necessary information for the search engine to perform its task. when the search engine is done, it writes to the swit ch response queue, and the frame engine uses the information provided in that queue for scheduling and forwarding. in performing its task, the search engine extracts and compresses the useful information from the 64-byte switch request. among the information extracted are the source and destination mac addres ses, the transmission and discard priorities, whether the frame is unicast or mult icast. requests are sent to the external sram switch database to locate the associated entries in th e external mct table. when all the information has been collected from external sram, the search engine has to compare the mac address on the current entry with the mac address for which it is searching. if it is not a match, the process is repeated on the internal mct table. all mct entries other t han the first of each linked list are maintained internal to the chip. if the desired mac address is still not found, then the result is ei ther learning (s ource mac address unknown) or flooding (desti nation mac address unknown). if the destination mac address belongs to a port trunk, then the trunk number is retrieved instead of the port number. but on which port of the trunk will the fr ame be transmitted? this is easily computed using a hash of the source and destination mac addresses. when all the information is co mpiled, the switch response is generated, as stated earlier. 5.3 search, learning, and aging 5.3.1 mac search the search block performs source ma c address and destination mac address searching. as we indicated earlier, if a match is not found, then the next entry in the linke d list must be examined, and so on until a match is found or the end of the list is reached. in port based vlan mode, a bitmap is used to determi ne whether the frame should be forwarded to the outgoing port. the bitmap is not dynamic. ports cannot enter and exit groups dynamically. the mac search block is also responsible for updatin g the source mac address timestamp, used for aging.
MVTX2801 data sheet 16 zarlink semiconductor inc. 5.3.2 learning the learning module learns new mac addresses and performs port change operations on the mct database. the goal of learning is to update this database as the networking environmen t changes over time. learning and port change will be performed based on memory slot availability only. 5.3.3 aging aging time is controlled by register 400h and 401h. the aging module scans and ages mct entries based on a programmable ?age out? time interval. as we indicated earlier, the search module updates the source mac addres s and vlan port association timestamps for each frame it processes. when an entry is ready to be aged, the entry is removed from the table. 5.3.4 data structure the mct data structure is used for searching for mac addr esses. the structure is maintained by hardware in the search engine. the database is essent ially a hash table, with collisions re solved by chaining. the database is partially external, and partially internal, as described earlier: the first mc t entry of each linked list is always located in the external sram, and the subsequent mcts are located internally. 6.0 frame engine 6.1 data forwarding summary ? enters the device at the rxmac, the rxdma will move the data from the mac rxfifo to the fdb. data is moved in 8-byte granules in conjunction with the scheme for the sram interface. ? a switch request is sent to the search engine. the search engine processes the switch request. ? a switch response is sent back to the frame engine and indicates whether the frame is unicast or multicast, and its destination port or ports. ? a transmission scheduling request is sent in the form of a signal notifying the txq manager. upon receiving a transmission scheduling request, the device will format an entry in the appropriate transmission scheduling queue (txsch q) or queues . there are 8 txsch queues for each gigabit port, one for each priority. creation of a queue entry either invo lves linking a new job to the appropriate linked list if unicast, or adding an entry to a physical queue if multicast. ? when the port is ready to accept the next frame, the txq manager will get the head-of-line (hol) entry of one of the txsch qs, according to the transmission scheduling algorithm (so as to ensure per-class quality of service). the unicast linked list and the multicas t queue for the same port-class pair are treated as one logical queue. ? the txdma will pull frame data from the memory and forward it granule-by-granule to the mac txfifo of the destination port. 6.2 frame engine details this section briefly describes the functions of ea ch of the modules of the MVTX2801 frame engine. 6.2.1 fcb manager the fcb manager allocates fcb handles to incoming fr ames, and releases fcb handles upon frame departure. the fcb manager is also responsible for enforcing buff er reservations and limits. the default values can be determined by referring to chapter 8. in addition, the fc b manager is responsible for buffer aging, and for linking unicast forwarding jobs to their correc t txsch q. the buffer aging can be enabl ed or disabled by the bootstrap pin and the aging time is defined in register fcbat.
MVTX2801 data sheet 17 zarlink semiconductor inc. 6.2.2 rx interface the rx interface is mainly responsible for communicating with the rxmac. it keeps track of the start and end of frame and frame status (good or bad). upon receiving an end of frame that is good, the rx interface makes a switch request. 6.2.3 rxdma the rxdma arbitrates among switch requests from each rx in terface. it also buffers the first 64 bytes of each frame for use by the search engine when the switch request has been made. 6.2.4 txq manager first, the txq manager checks the per- class queue status and global reserved resource situation, and using this information, makes the frame dropping decision after receiving a switch response. if the decision is not to drop, the txq manager requests that the fcb manager link the unicast frame's fcb to the correct per-port-per-class txq. if multicast, the txq manager writes to the multicast queue for that port and class. the txq manager can also trigger source port flow control for the incoming frame's source if that port is flow control enabled. second, the txq manager handles transmission scheduling; it schedules transmissi on among the queues representing different classes for a port. once a frame has been scheduled, the txq manager reads the fcb information and writes to the correct port control module. 6.3 port control the port control module calculates the sram read addres s for the frame currently being transmitted. it also writes start of frame information and an end of frame flag to th e mac txfifo. when transmission is done, the port control module requests that the buffer be released. 6.4 txdma the txdma multiplexes data and address from port control, and arbitrates among buffer release requests from the port control modules. 7.0 quality of se rvice and flow control 7.1 model quality of service (qos) is an all-encom passing term for which different people have different interpretations. in this chapter, by quality of service assurances, we mean the allocation of chip resources so as to meet the latency and bandwidth requirements associat ed with each traffic class. we do not pres uppose anything about the offered traffic pattern. if the traffic load is light, then ensuring quality of service is stra ightforward. but if the traffic load is heavy, t he MVTX2801 must intelligently allocate resources so as to assure q uality of service for high priority data. we assume that the network manager knows his applications, su ch as voice, file transfer , or web browsing, and their relative importance. the manager can then subdivide the app lications into classes and set up a service contract with each. the contract may consist of bandwidth or latency assurances per class. someti mes it may even reflect an estimate of the traffic mix offered to th e switch, though this is not required. the table below shows examples of qos applications with eigh t transmission priorities, including best effort traffic for which we provide no bandwidth or latency assurances.
MVTX2801 data sheet 18 zarlink semiconductor inc. it is possible that a class of traffic may attempt to monopolize system resources by sending data at a rate in excess of the contractually assured bandwidth for that class. a we ll-behaved class offers traffic at a rate no greater than the agreed-upon rate. by contrast, a misbehaving class offers traffic that exceeds the agreed-upon rate. a misbehaving class is formed from an aggregation of misbehavi ng microflows. to achieve high lin k utilization, a misbehaving class is allowed to use any idle bandwidth. however, the quality of service (qos) received by well-b ehaved classes must never suffer. as table 1 illustrates, each traffic class may have its own distinct properties and appl ications. as shown, classes may receive bandwidth assurances or latency bounds. in th e example, p7, the highest tr ansmission class, requires that all frames be transmitted within 0.2 ms, and rece ives 30% of the 1 gbps of bandwidth at that port. best-effort (p1-p0) traffic forms a lower tier of service that only receives ba ndwidth when none of the other classes have any traffi c to offer. in addition, each transmission class has two subclasses, high-drop and low-drop. well-behaved users should not lose packets. but poorly beh aved users, users who send data at too high a rate, will encounter frame loss, and the first to be discarded will be hi gh-drop. of course, if this is insufficient to resolv e the congestion, eventually some low-drop frames are dropped as well. table 1 shows that different types of applications may be pl aced in different boxes in the traffic table. for example, web search may fit into the category of high-loss, high-laten cy-tolerant traffic, whereas vo ip fits into the category of low-loss, low-la tency traffic. class example assured bandwidth (user defined) low drop subclass (if class is oversubscribed, these packets are the last to be dropped.) high drop subclass (if class is oversubscribed, these packets are the first to be dropped.) highest transmission priorities, p7 latency < 200 s 300 mbps sample application: control information highest transmission priorities, p6 latency < 200 s 200 mbps sample applications: phone calls; circuit emulation sample application: training video; other multimedia middle transmission priorities, p5 latency < 400 s 125 mbps sample application: interactive activities sample application: non-critical interactive activities middle transmission priorities, p4 latency < 800 s 250 mbps sample application: web business low transmission priorities, p3 latency < 1600 s 80 mbps sample application: file backups low transmission priorities, p2 latency < 3200 s 45 mbps sample application: email sample application: web research best effort, p1-p0 - sample application: casual web browsing total 1 gbps table 1 - two-dimensional world traffic
MVTX2801 data sheet 19 zarlink semiconductor inc. 7.2 four qos configurations there are four basic pieces to qos scheduling in the mv tx2801: strict priority (sp), delay bound, weighted fair queuing (wfq), and best effort (be). using these four piec es, there are four different modes of operation, as shown in table 2. the default configuration is six delay-bounded queues and two best-effort queues. the delay bounds per class are 0.16 ms for p7 and p6, 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. best effort traffic is only served when there is no delay-bounded traffic to be served. p1 has strict priority over p0. we have a second configuration in which there are two st rict priority queues, four delay bounded queues, and two best effort queues. the delay bounds per class are 0.32 ms for p5, 0.64 ms for p4, 1.28 ms for p3, and 2.56 ms for p2. if the user is to choose this config uration, it is important that p7-p6 (sp) traffic be either policed or implicitly bounded (e.g. if the incoming sp traffic is very light and predictably patterned). strict priority traffic, if not admission-controlled at a prior stage to the MVTX2801, can have an adverse effe ct on all other classes' performance. p7 and p6 are both sp classes, and p7 has strict priority over p6. the third configuration contains two strict priority queu es and six queues receiving a bandwidth partition via wfq. as in the second configuration, strict prio rity traffic needs to be carefully controlled. in the fourth configuration, all queues are served using a wfq service discipline 7.3 delay bound in the absence of a sophisticated qos server and signaling protocol, the mv tx2801 may not be assured of the mix of incoming traffic ahead of time. to cope with this un certainty, our delay assurance algorithm dynamically adjusts its scheduling and dropping criteria, guided by the queue occupancies and the due dates of their head-of-line (hol) frames. as a result, we assure latency bounds for all admit ted frames with high confidenc e, even in the presence of system-wide congestion. our algorithm identifies misbehaving classes and intelligently discards frames at no detriment to well-behaved classes. our algorithm also differentiates between high-drop and low-drop traffic with a weighted random early drop (wred) approach. random earl y dropping prevents conges tion by randomly dropping a percentage of high- drop frames even before the chip's buffers are co mpletely full, while still largely sparing low-drop frames. this allows high-drop frames to be di scarded early, as a sacrifice for future low-drop frames. finally, the delay bound algorithm also achi eves bandwidth partitioning among classes. 7.4 strict priority and best effort when strict priority is part of the sc heduling algorithm, if a queue has even o ne frame to transmit, it goes first. two of our four qos configurations include st rict priority queues. the goal is for stri ct priority classes to be used for ietf expedited forwarding (ef), where performance guarantees are required. as we have indicated, it is important that strict priority traffic be either policed or implicitly b ounded, so as to keep from harming other traffic classes. when best effort is part of the scheduling algorithm, a q ueue only receives bandwidth when none of the other classes have any traffic to offer. two of our four qos configurat ions include best effort queues. the goal is for best effort p7 p6 p5 p4 p3 p2 p1 p0 op1 (default) delay bound be op2 sp delay bound be op3 sp wfq op4 wfq table 2 - four qos configurations per port
MVTX2801 data sheet 20 zarlink semiconductor inc. classes to be used for non-essential traffic, because we provide no assurances about best effort performance. however, in a typical network setting, much best effort traffic will indeed be transmitted, and with an adequate degree of expediency. because we do not provide any delay assurances for best effort traffic, we do not enforce latency by dropping best effort traffic. furthermore, because we assume that strict priority traffic is carefully controlled before entering the MVTX2801, we do not enforce a fair bandwidth partition by dropping strict priority traffic. to summarize, dropping to enforce quality of service (i.e. bandwidth or delay) does not ap ply to strict priority or best effort queues. we only drop frames from best effort and stri ct priority queues when global buffer resources become scarce. 7.5 weighted fair queuing in some environments - for example, in an environment in which delay assurances are not required, but precise bandwidth partitioning on small time scales is essent ial (wfq may be preferable to a delay-bounded scheduling discipline). the MVTX2801 provides the user with a wf q option with the understandi ng that delay assurances cannot be provided if the incoming traffic pattern is unc ontrolled. the user sets eight wfq ?weights? such that all weights are whole numbers and sum to 64. this provides per-class bandwidth partitioning with error within 2%. in wfq mode, though we do not assure frame latency, the MVTX2801 still retain s a set of dropping rules that helps to prevent congestion and trigger higher level protocol end-to-end flow control. as before, when strict priori ty is combined with wfq, we do not have sp ecial dropping rules for the strict priority queues, because the input traffic pattern is assumed to be carefully controlled at a pr ior stage. however, we do indeed drop frames from sp queues for global buffer ma nagement purposes. in addition, queues p1 and p0 are treated as best effort from a dropping perspective, th ough they still are assured a pe rcentage of ba ndwidth from a wfq scheduling perspective. what this means is that th ese particular queues are on ly affected by dropping when the global buffer count becomes low. 7.6 shaper although traffic shaping is not a primary function of the MVTX2801, the chip does implement a shaper for expedited forwarding (ef). our goal in shaping is to control the peak and average rate of traffic exiting the MVTX2801. shaping is limited to class p6 (the second highest priority). this means that class p6 will be the class used for ef traffic. (by contrast, we assume class p7 will be used for co ntrol packets only.) if sh aping is enabled for p6 , then p6 traffic must be scheduled using strict priority. with reference to table 2, only the middle two qos configurations may be used. peak rate is set using a programmable whole number, no greater than 64 (register qos-credit_c6_gn). for example, if the setting is 32, then the peak rate for shaped traffic is 32/64 x 1000 mbps = 500 mbps. average rate is also a programmable whole number, no greater than 64, a nd no greater than the peak rate. for example, if the setting is 16, then the average rate for shaped traffic is (16/64) x 1000 mbps = 250 mbps. as a consequence of the above settings in our example, shape d traffic will exit the MVTX2801 at a rate always less than 500 mbps, and averaging no greater than 250 mbps. also, when shaping is enabled, it is possible for a p6 queue to explode in length if fed by a greedy source. the reason is that a shaper is by definition not work-conserving; that is, it may hold back from sending a packet even if the line is idle. though we do have global resource management, we do nothing to prevent this situation locally. we assume sp traffic is policed at a prior stage to the MVTX2801. 7.7 wred drop threshold management support to avoid congestion, the weighted random early detection (wred) logic drops packets according to specified parameters. the following table summarizes the behavior of the wred logic.
MVTX2801 data sheet 21 zarlink semiconductor inc. in the table, |px| is the byte count in queue px. the wred logic has three drop levels, depending on the value of n, which is based on the number of bytes in the priority queues. if delay bound scheduling is used, n equals 16|p7| + 16|p6| + 8|p5| + 4|p4| + 2|p3| + |p2|. if wfq scheduling is used, n equals |p7| + |p6| + |p5| + |p4| + |p3| + |p2|. each drop level has defined high-drop and low-drop percen tages, which indicate the percentage of high-drop and low-drop packets that will be dropped at that level. the x, y, and z percent paramete rs can be programmed using the registers rdrc0 and rdrc1. parameters a-f are the by te count thresholds for each priority queue, and are also programmable. when using delay bound scheduling, the values selected for a-f also control the approximate bandwidth partition among the traffic classes; see application note. 7.8 buffer management because the number of frame data buffer (fdb) slots is a scarce resource, and because we want to ensure that one misbehaving source port or class cannot harm the performance of a well-behaved source port or class, we introduce the concept of buffer management into the MVTX2801. our buffer managem ent scheme is designed to divide the total buffer space into numerous reserved regions and one shared pool (see figure 4). as shown in the figure, the fdb pool is divided into se veral parts. a reserved region for temporary frames stores frames prior to receiving a switch response. such a temp orary region is necessary, because when the frame first enters the MVTX2801, its destination port and class are as yet unknown, and so the decision to drop or not needs to be temporarily postponed. this ensur es that every frame can be received fi rst before subjecting it to the frame drop discipline after classifying. six reserved sections, one for each of the highest six prio rity classes, ensure a programmable number of fdb slots per class. the lowest two classes do not receive any buffer reservation. another segment of the fdb reserves space for each of th e 4 ports. these source port buffer reservations are programmable. these 8 reserved regions make sure th at no well-behaved source port can be blocked by another misbehaving source port. in addition, there is a shared pool , which can store any type of frame. the registers related to the buffer management logic are: ? prg- port reservation for gigabit ports ? sfcb- share fcb size ? c2rs- class 2 reserved size ? c3rs- class 3 reserved size ? c4rs- class 4 reserved size ? c5rs- class 5 reserved size ? c6rs- class 6 reserved size ? c7rs- class 7 reserved size p7 p6 p5 p4 p3 p2 high drop low drop level 1 n > 240 |p7| > a kb |p6| > b kb |p5| > c kb |p4| > d kb |p3| > e kb |p2| > f kb x% 0% level 2 n > 280 y% z% level 3 n > 320 100% 100% table 3 - wred dropping scheme
MVTX2801 data sheet 22 zarlink semiconductor inc. figure 4 - buffer partition scheme used in the MVTX2801 7.8.1 dropping when buffers are scarce summarizing the two examples of local dr opping discussed earlier in this chapter: ? if a queue is a delay-bounded queue, we have a multilev el wred drop scheme, designed to control delay and partition bandwidth in case of congestion. ? if a queue is a wfq-scheduled queue, we have a mult ilevel wred drop scheme, designed to prevent congestion. in addition to these reasons for dropping, the mvtx2 801 also drops frames when global buffer space becomes scarce. the function of buffer management is to ensure that such droppings cause as little blocking as possible. 7.9 flow control basics because frame loss is unacceptable for some applications, the MVTX2801 provides a flow control option. when flow control is enabled, scarcity of buffer space in the switch ma y trigger a flow control signal; this signal tells a source port, sending a packet to this switch, to temporarily hold off. while flow control offers the clear benefit of no packet loss , it also introduces a problem for quality of service. when a source port receives an ethernet flow control signal, all microflows originating at that port, well-behaved or not, are halted. a single packet destined for a congested output can block other pack ets destined for uncongested outputs. the resulting head-of-line blocking phenomenon means th at quality of service cannot be assured with high confidence when flow control is enabled. in the MVTX2801, each source port can independently have flow control enabled or disabled. for flow control enabled ports, by default all frames are treated as lowest priority during transmission scheduling. this is done so that those frames are not exposed to the wred dropping scheme. frames from flow control enabled ports feed to only one queue at the destination, the queue of lowest priori ty. what this means is that if flow control is enabled for a given source po rt, then we can guarantee that no packets originating from that port will be lost, but at the possible expense of minimum bandwidth or maximum delay assur ances. in addition, these ?downgraded? frames may only use the shared pool or the per-source reserved pool in the fdb; frames from flow control enabled sources may not use reserved fdb slots for the highest six classes (p2-p7). the MVTX2801 does provide a system-wide option of permitting normal qos scheduling (and buffer use) for frames shared pool s temporary reservation r tmp per-class reservations r p7 , r p6 ... r p2 per-source reservations 8 . r 1g
MVTX2801 data sheet 23 zarlink semiconductor inc. originating from flow control enabled ports. when this prog rammable option is active, it is possible that some packets may be dropped, even though flow control is on. the reas on is that intelligent packet dropping is a major component of the MVTX2801's approach to ensuring bounded del ay and minimum bandwidth for high priority flows. 7.9.1 unicast flow control for unicast frames, flow contro l is triggered by source port resource availability. reca ll that the mvtx 2801's buffer management scheme allocates a reserved number of fdb slot s for each source port. if a programmed number of a source port's reserved fdb slots have been used, then flow co ntrol xoff is triggered. xon is triggered when a port is currently being flow controlled, and all of that port's reserved fdb slots have been released. note that the MVTX2801's per-source-port fdb reservations assure that a source port that sends a single frame to a congested destination will not be flow controlled. 7.9.2 multicast flow control when port based vlan is not used, a global buffer counter (64 packets) triggers flow control for multicast frames. when the system exceeds a programmable threshold of mult icast packets, xoff is trig gered. xon is triggered when the system returns below this threshold. mcc register pr ograms the threshold. when port based vlan is used, each vlan has a global buffer counter. in addition, each source port has an 8-bit port map record ing which port or ports of the multicast frame's fanout were congested at the time xoff was triggered. all ports are cont inuously monitored for congestion, and a port is identified as uncongested when its queue occupancy falls below a fix ed threshold. when all those ports that were originally marked as congested in the port map hav e become uncongested, then xon is triggered, and the 8-bit vector is reset to zero. the MVTX2801 also provides the option of disabling vlan multicast flow control. note: if port flow control is on, qos pe rformance will be affected. to determine the most ef ficient way to program, please refer to the qo s application note. 7.10 mapping to ietf diffserv classes the mapping between priority classes discussed in this chapter and elsewhere is shown below. as the table illustrates, p7 is used solely for netw ork management (nm) frames. p6 is used for expedited forwarding service (ef). classes p2 through p5 correspond to an assured forwarding (af) group of size 4. finally, p0 and p1 are two best effort (be) classes. features of the MVTX2801 that correspond to the requir ements of their associated ietf classes are summarized in the table below. MVTX2801 p7 p6 p5 p4 p3 p2 p1 p0 ietf nm ef af0 af1 af2 af3 be0 be1 table 4 - mapping between MVTX2801 and ietf diffserv classes for gigabit ports
MVTX2801 data sheet 24 zarlink semiconductor inc. 8.0 port trunking 8.1 features and restrictions a port group (i.e. trunk) can include up to 4 physical ports, but all of the ports in a group must be in the same MVTX2801. the MVTX2801 provides several pre-assigned trunk group options, containing as many as 4 ports per group, or alternatively, as many as 4 total groups. load distribution among the ports in a trunk for unicast is performed using hashing based on source mac address and destination mac address. the other options includ e source mac address only, destination mac address only. load distribution for multicast is performed similarly. if a vlan includes any of the ports in a trunk group, all th e ports in that trunk group should be in the same vlan member map. the MVTX2801 also provides a safe fail-over mode for port trunking automatically. if one of the ports in the trunking group goes down, the MVTX2801 will automati cally redistribute the traffic over to the remaining port s in the trunk in unmanaged mode. in managed mode, the software can perform similar tasks. 8.2 unicast packet forwarding the search engine finds the destination mct entry, and if the status field says that the destination address found belongs to a trunk, then the group number is retrieved inst ead of the port number. in addition, if the source address belongs to a trunk, then the source port's trunk membership register is checked to determine if the address has moved. a hash key is used to determine the appropriate forwardi ng port, based on some combination of the source and destination mac addresses for the current packet. network management (nm) and expedited forwarding (ef) ? global buffer reservation for nm and ef ? shaper for ef traffic ? option of strict priority scheduling ? no dropping if admission controlled assured forwarding (af) ? four af classes ? programmable bandwidth partition, with option of wfq service ? option of delay-bounded service keeps delay under fixed levels even if not admission-controlled ? random early discard, with programmable levels ? global buffer reservation for each af class best effort (be) ? two be classes ? service only when other queues are idle means that qos not adversely affected ? random early discard, with programmable levels ? traffic from flow control enabled ports automatically classified as be table 5 - MVTX2801 features enabling ietf diffserv standards
MVTX2801 data sheet 25 zarlink semiconductor inc. the search engine retrieves the vlan member ports from the vlan index table, which consists of 4k entries. the search engine retrieves the vlan member ports from the ingress port's vlan map. based on the destination mac address, the search engine determines the egress port from the mct database. if the egress port is a member of a trunk group, the packet can be distributed to the ot her members of that trunk group. the vlan map is used to check whether the egress port is a member of the vlan, base d on the ingress port. if it is a member, the packet is forwarded otherwise it is discarded. 8.3 multicast packet forwarding for multicast packet forwarding, the devic e must determine the proper set of ports from which to transmit the packet based on the vlan index and hash key. two functions are required in order to distribute multic ast packets to the appropriat e destination ports in a port trunking environment. ? determining one forwarding port per group. ? for multicast packets, all but one port per group, the forwarding port, must be excluded. 8.4 preventing multicast packets from looping back to the source trunk the search engine needs to prevent a mult icast packet from sending to a port that is in the same trunk group with the source port. this is because, when we select the primary forwarding port for each group, we do not take the source port into account. to prevent this, we simply apply on e additional filter, so as to block that forwarding port for this multicast packet. 9.0 led interface 9.1 introduction the MVTX2801 led block provides two interfaces: a serial output channel, and a parallel time-division interface. the serial output channel provides port status informati on from the MVTX2801 chip in a continuous serial stream. this means that a low cost external device must be used to decode the serial data and to drive an led array for display. by contrast, the parallel time-division interface supports a glueless led module. indeed , the parallel interface can directly drive low-current leds without any extra logic. the pin led_pm is used to select serial or parallel mode. for some led signals, the interface also provides a blin king option. blinking may be enabled for led signals txd, rxd, col, and fc (to be described la ter). the pin led_blink is used to enab le blinking, and the blinking frequency is around 160 ms. 9.2 serial mode in serial mode, the fo llowing pins are utilized: ? led_synco - a sync pulse that defines the boundary between status frames ? led_clko - the clock signal ? led_do - a continuous serial stream of data for all status leds that repeats once every frame time in each cycle (one frame of status information, or one sy nc pulse), 16x8 bits of data are transmitted on the led_do signal. the sequence of transmission of data bits is as shown in the figure below:
MVTX2801 data sheet 26 zarlink semiconductor inc. table 6 - timing diagram for serial mode in led interface the status bits shown in here are flow control (fc), tr ansmitting data (txd), rece iving data (rxd), link up (lnk), speed (sp0 and sp1), full duplex (fdx), and collision (col). note that sp[1:0] is defined as 10 for 1 gbps, 01 for 100 mbps, and 00 for 10 mbps. also note that u0-u7 represent user-d efined sub-frames in which additional status information may be embedded. we will see later that the MVTX2801 provid es registers that can be written by the cpu to indicate this additional status information as it becomes available. 9.3 parallel mode in parallel mode, the fo llowing pins are utilized: ? led_port_sel[3:0] - indicates which of the 4 gigabit port status bytes is being read out ? led_port_sel[7:4] - no use. ? led_port_sel[9:8] - indicates which of the 2 user-defined status bytes is being read out ? led_byteout_[7:0] - provides 8 bits for 4 different por t status indicators. note that these bits are active low. by default, the system is in parallel mode. in parallel mode, the 10 status bytes are scan ned in a continuous loop, with one byte read out per clock cycle, and the appropriate port select bit asserted. 9.4 led control registers an led control register can be used for programming the led clock rate, sample hold time, and pattern in parallel mode. in addition, the MVTX2801 provides 8 registers calle d leduser[7:0] for user-defined status bytes. during operation, the cpu can write va lues to these registers, wh ich will be read out to the le d interface output (serial or parallel). only leduser[1:0] are used in parallel mode. the cont ent of the leduser registers will be sent out by the led serial shift logic, or in parallel mode, a byte at a time. because in parallel mode there are only two user-defined registers, leduser[7:2] is shared with ledsig[7:2]. for ledsig[j], where j = 2, 3, ..., 6, the correspon ding register is used for programming the led pin led_byteout_[j]. the format is as follows: 7430 col fdx sp1 sp0 col fdx sp1 sp0 p0 info p1 info p2 info p3 info p4 info p5 info p6 info p7 info u0 u1 u2 u3 u4 u5 u6 u7 le_synco le_do le_clko fc txd rxd lnk sp0 sp1 fdx col 07 6 5 4 3 2 1
MVTX2801 data sheet 27 zarlink semiconductor inc. bits [3:0] signal polarity: 0: do not invert polarity (high true) 1: invert polarity bits [7:4] signal select: 0: do not select 1: select the corresponding bit for j = 2, 3, ..., 5, the value of led_byteout_[j] equals the logical and of all selected bits. for j = 6, the value is equal to the logical or. therefore, the programmable leds ig[5:2] registers allow any conjunctive formula including any of the 4 status bits (col, fdx, sp1, sp0) or thei r negations to be sent to the led_byteout_[5:2] pins. similarly, the programmable ledsig[6] register allows any disjunctive formula including any of the 4 status bits or their negations to be sent to pin led_byteout_[6]. ledsig[7] is used for programming both led_byteout_[1] and led_byteout _[0]. as we will see, it has other functions as well. the format is as follows: 7430 gp rxd txd fc p6 rxd txd fc bits [7] ? global output polarity: this bit cont rols the output polarity of all led_byteout_ and led_port_sel pins. (default 0) - 0: do not invert polarity (led _byteout_[7:0] are high activated; led_port_sel[9:0] are low activated) - 1: invert polarity (led_byteout_[7:0] are low activated; led_port_sel[9:0] are high activated) bits [6:4] ? signal select: - 0: do not select - 1: select the corresponding bit ? the value of led_byteout_[1] equals th e logical or of all selected bits. (default 110) bit [3] ? polarity contro l of led_byteout_[6] (default 0) - 0: do not invert -1: invert bits [2:0] ? signal select: - 0: do not select - 1: select the corresponding bit ? the value of led_byteout_[0] equals th e logical or of all selected bits. (default 001)
MVTX2801 data sheet 28 zarlink semiconductor inc. 10.0 register definition 10.1 register description register description cpu addr (hex) r/w i 2 c addr (hex) default notes 0. ethernet port control registers - substitute [n] with port number (0..3) ecr1p?n? port control register 1 for port n 000 + 2n r/w 000+2n c0 ecr2p?n? port control register 2 for port n 001 + 2n r/w 001+2n 00 ggcontrol0 extra gigabit port control -port 0,1 012 r/w n/a 00 ggcontrol1 extra gigabit port control -port 2,3 013 r/w n/a 00 activelink active link status port 3:0 016 r/w n/a 00 1. vlan control registers - substitute [n] with port number (0..3) avtcl vlan type code register low 100 r/w 012 00 avtch vlan type code register high 101 r/w 013 81 pvmap?n?_0 port ?n? configuration register 0 102 + 4n r/w 014+4n ff pvmap?n?_3 port ?n? configuration register 3 105 + 4n r/w 017+4n 00 pvmode vlan operating mode 126 r/w 038 00 2. trunk control registers trunk0_mode trunk group 0 mode 207 r/w 039 00 trunk1_mode trunk group 1 mode 20e r/w 03a 00 3. cpu port configuration tx_age transmission queue aging time 312 r/w 03b 08 4. search engine configurations agetime_low mac address aging time low 400 r/w 03c 2c agetime_high mac address aging time high 401 r/w 03d 00 se_opmode search engine operation mode 403 r/w na 00 5. buffer control and qos control fcbat fcb aging timer 500 r/w 03e ff qosc qos control 501 r/w 03f 00 fcr flooding control register 502 r/w 040 08 avpml vlan priority map low 503 r/w 041 88 avpmm vlan priority map middle 504 r/w 042 c6 avpmh vlan priority map high 505 r/w 043 fa tospml tos priority map low 506 r/w 044 88 tospmm tos priority map middle 507 r/w 045 c6 table 7 - MVTX2801 register description
MVTX2801 data sheet 29 zarlink semiconductor inc. tospmh tos priority map high 508 r/w 046 fa avdm vlan discard map 509 r/w 047 00 tosdml tos discard map 50a r/w 048 00 bmrc broadcast/multicast rate control 50b r/w 049 00 ucc unicast congestion control 50c r/w 04a 07 mcc multicast congestion control 50d r/w 04b 48 pr100 port reservation for 10/100 ports 50e r/w 04c 00 prg port reservation for giga ports 50f r/w 04d 26 sfcb share fcb size 510 r/w 04e 37 c2rs class 2 reserved size 511 r/w 04f 00 c3rs class 3 reserved size 512 r/w 050 00 c4rs class 4 reserved size 513 r/w 051 00 c5rs class 5 reserved size 514 r/w 052 00 c6rs class 6 reserved size 515 r/w 053 00 c7rs class 7 reserved size 516 r/w 054 00 qosc?n? qos control (n=0 - 2f) 517-546 r/w 055-084 qosc?n? qos control (n=30 - 82) 547-599 r/w na rdrc0 wred rate control 0 59a r/w 085 8e rdrc1 wred rate control 1 59b r/w 086 68 6. misc configuration register mii_op0 mii register option 0 600 r/w 0b1 00 mii_op1 mii register option 1 601 r/w 0b2 00 fen feature registers 602 r/w 0b3 10 miic0 mii command register 0 603 r/w n/a 00 miic1 mii command register 1 604 r/w n/a 00 miic2 mii command register 2 605 r/w n/a 00 miic3 mii command register 3 606 r/w n/a 00 miid0 mii data register 0 607 ro n/a 00 miid1 mii data register 1 608 ro n/a 00 led led control register 609 r/w 0b4 38 checksum eeprom checksum register 60b r/w 0c5 00 leduser0 led user define register 0 60c r/w 0bb 00 leduser1 led user define register 1 60d r/w 0bc 00 register description cpu addr (hex) r/w i 2 c addr (hex) default notes table 7 - MVTX2801 register description (continued)
MVTX2801 data sheet 30 zarlink semiconductor inc. leduser2 led user define reg. 2/led_byte pin 2 60e r/w 0bd 80 leduser3 led user define reg. 3/led_byte pin 3 60f r/w 0be 33 leduser4 led user define reg. 4/led_byte pin 4 610 r/w 0bf 32 leduser5 led user define reg. 5/led_byte pin 5 611 r/w 0c0 20 leduser6 led user define reg. 6/led_byte pin 6 612 r/w 0c1 40 leduser7 led user define reg. 7/led_byte pin 1 & 0 613 r/w 0c2 61 miinp0 mii next page data register0 614 r/w 0c3 00 miinp1 mii next page data register1 615 r/w 0c4 00 e. test group control dtsrl test register low e00 r/w n/a 00 dtsrm test register medium e01 r/w n/a 01 dtsrh test register high e02 r/w n/a 00 tdrb0 test mux read back register [7:0] e03 ro n/a tdrb1 test mux read back register [15:8] e04 ro n/a dtcr test counter register e05 r/w n/a 00 mask0 mask timeout 0 e06 r/w 0b6 00 mask1 mask timeout 1 e07 r/w 0b7 00 mask2 mask timeout 2 e08 r/w 0b8 00 mask3 mask timeout 3 e09 r/w 0b9 00 mask4 mask timeout 4 e0a r/w 0ba 00 f. device configuration register gcr global control register f00 r/w n/a 00 dcr device status and signature register f01 ro n/a dcr01 gigabit port0 port1 status register f02 ro na dcr23 gigabit port2 port3 status register f03 ro na dcr45 gigabit port4 port5 status register f04 ro na dcr67 gigabit port6 port7 status register f05 ro na dpst device port status register f06 r/w n/a 00 dtst data read back register f07 ro n/a pllcr pll control register f08 r/w n/a 00 lclkcr lclk control register f09 r/w n/a 00 bclkcr bclk control register f0a r/w n/a 00 register description cpu addr (hex) r/w i 2 c addr (hex) default notes table 7 - MVTX2801 register description (continued)
MVTX2801 data sheet 31 zarlink semiconductor inc. note : 1. se = search engine 2. fe = frame engine 3. pgs = port group01, 23, 45, and 67 4. mc = mac control 5. tm = timer 10.2 group 0 address - mac ports group 10.2.1 ecr1pn: po rt n control register i 2 c address h00+2n; serial interface address: h000+ 2n (n=0 to 3) (for the 2600 it is different) accessed by serial interface and i 2 c (r/w) bstrrb0 boot strap read back register 0 f0b ro n/a bstrrb1 boot strap read back register 1 f0c ro n/a bstrrb2 boot strap read back register 2 f0d ro n/a bstrrb3 boot strap read back register 3 f0e ro n/a bstrrb4 boot strap read back register 4 f0f ro n/a bstrrb5 boot strap read back register 5 f10 ro n/a da da register fff ro n/a da 76543210 sp state a-fc port mode bit [4:0] ? port mode (default 2'b00) bit [4:3] - 00 - automatic enable auto-negotiation - this enables hardware state machine for auto-negotiation. - 01 - limited disable auto-negotiation - this disables hardware for speed auto-negotiation. hardware polls mii for link status. - 10 - link down - force link down (disable the port). does not talk to phy. - 11 - link up - does not talk to phy. user erc1 [2:0] for config. bit [2] - 1 - 10mbps (default 1'b0) - 0 - 100mbps ? bit 2 is used only when the port is in mii (10/100) mode. bit [1] - 1 - half duplex (do not use) (default 1'b0) - 0 - full duplex register description cpu addr (hex) r/w i 2 c addr (hex) default notes table 7 - MVTX2801 register description (continued)
MVTX2801 data sheet 32 zarlink semiconductor inc. 10.2.2 ecr2pn: po rt n control register i 2 c address: 01+2n; serial interface address:h001+2n (n=0to3) accessed by serial interface (r/w) bit [0] - 1 - flow control off (default 1'b0) - 0 - flow control on ? when flow control is on: ? in full duplex mode, the mac transmitter s ends flow control frames when necessary. the mac receiver interprets and processes incoming flow control frames. the flow control frame received counter is incremented whenever a flow control frame is received. ? when flow control is off: ? in full duplex mode, the mac transmitter does not send flow control frames. the mac receiver does not interpret or process the flow control frames. the flow control frame receiver counter is not incremented. bit [5] ? asymmetric flow control enable. - 0 - disable asymmetric flow control - 1 - enable asymme tric flow control ? when this bit is set, and flow control is on (bit [0] = 0), don't send out a flow control frame. but mac receiver interprets and process flow control frames. (default is 0) bit [7:6] - ss - spanning tree state (802.1d spanning tree protocol). (default 2'b11) - 00 - blocking: frame is dropped - 01 - listening: frame is dropped - 10 - learning: frame is dropped. source mac address is learned. - 11 - forwarding: frame is forwarded. source mac address is learned. 765 3210 security en disl ftf futf bit[0]: ? filter untagged frame (default 0) ?0: disable ? 1: enable - all untagged frames from this port are discarded or follow security option when security is enable bit[1]: ? filter tag frame (default 0) ?0: disable ? 1: enable - all tagged frames from this port are discarded or follow security option when security is enable bit[2]: ? learning disable (default 0) ? 0: learning is enabled on this port ? 1: learning is disabled on this port bit [5:3] ? reserved
MVTX2801 data sheet 33 zarlink semiconductor inc. 10.2.3 ggcontrol 0- extra giga port control serial interface address:h012 accessed by and serial interface (r/w) 10.2.4 ggcontrol 1- extra giga port control serial interface address:h013 bit[7:6] ? security enable (default 00). the MVTX2801 c hecks the incoming data for one of the following conditions: ? if the source mac address of the incoming packet is in the mac table and is defined as secure address but the ingress port is not the same as the port associated with the mac address in the mac table. ? a mac address is defined as secure when its ent ry at mac table has static status and bit 0 is set to 1. mac address bit 0 (the first bit transmi tted) indicates whether the address is unicast or multicast. as source addresses are always unicast bit 0 is not used (always 0). MVTX2801 uses this bit to define secure mac addresses. ? if the port is set as learning disable and the source mac address of the incoming packet is not defined in the mac address table. ? if the port is configured to filter untagged fram es and an untagged frame arrives or if the port is configured to filter tagged frames and a tagged frame arrives. ? if one of these three conditions occurs, th e packet will be handled according to one of the following specified options: - 00 - disable port security - 01 - enable port security. port will be disabled when security violation is detected -10 - n/a -11 - n/a 76543210 mii1 rst1 mii0 rst0 bit[0]: ? reset giga port 0 (default is 0) - 0: normal operation - 1: reset gigabit port 0. bit[1]: ? giga port 0 use mii interface (10/100m) (default is 0) - 0: gigabit port operation at 1000m mode - 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved -must be '0' (default 0) bit[4]: ? reset giga port 1 (default 0) - 0: normal operation - 1: reset gigabit port 1. bit[5]: ? giga port 1 use mii interface (10/100m) (default 0) - 0: gigabit port operation at 1000m mode - 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' (default 0)
MVTX2801 data sheet 34 zarlink semiconductor inc. accessed by cpu and serial interface (r/w) 10.3 group 1 address - vlan group 10.3.1 avtcl - vlan type code register low i 2 c address h12; serial interface address:h100 accessed by serial interface and i 2 c (r/w) 10.3.2 avtch - vlan type code register high i 2 c address h13; serial interface address:h101 accessed by serial interface and i 2 c (r/w) 10.3.3 pvmap00_0 - port 00 configuration register 0 i 2 c address h14, serial interface address:h102) accessed by serial interface and i 2 c (r/w) port based vlan mode 76543210 mii3 rst3 mii2 rst2 bit[0]: ? reset giga port 2 default is 0 - 0: normal operation - 1: reset gigabit port 2 bit[1]: ? giga port 2 use mii interface (10/100m) default is 0 - 0: gigabit port operation at 1000m mode - 1: gigabit port operation at 10/100m mode (mii) bit[3:2]: ? reserved - must be '0' (default '0' ) bit[3]: ? reserved - must be '0' bit[4]: ? reset giga port 3 default is 0 - 0: normal operation - 1: reset gigabit port 3. bit[5]: ? giga port 3 use mii interface (10/100m) default is 0 - 0: gigabit port operation at 1000m mode - 1: gigabit port operation at 10/100m mode (mii) bit[7:6]: ? reserved - must be '0' (default '0') bit[7:0]: ? vlantype_low: lower 8 bits of the vlan type code (default 00) bit [7:0] ? vlantype_high: upper 8 bits of the vlan type code (default is 81)
MVTX2801 data sheet 35 zarlink semiconductor inc. this register indicates the legal egress ports. example: a ?1? on bit 3 means that packets arriving on port 0 can be sent to port 3. a ?0? on bit 3 means that any packet destin ed to port 3 will be discarded. 10.3.4 p pvmap00_3 - port 00 configuration register 3 i 2 c address h17, serial interface address:h105 accessed by serial interface and i 2 c (r/w) port based mode port vlan map pvmap00_0,3 i 2 c address h14, 17; serial interface address:h102, 105) see above format pvmap01_0,3 i 2 c address h18, 1b; serial interface address:h106, 109) see above format bit[3:0]: ? vlan mask for ports 3 to 0 (default f) -0 - disable -1 - enable bit[7:4]: ? reserve (default f) 765 3 21 0 fp en drop default tx priority fnt reserved bit [1:0]: ? reserved (default 0) bit [2]: ? force untagout (default 0) -0 disable - 1 force untag output all packets transmitted from this port are untagge d. this register is used when this port is connected to legacy equipment that does not support vlan tagging. bit [5:3]: ? fixed transmit priority. used when bit[7] = 1 (default 0) - 000 transmit priority level 0 (lowest) - 001 transmit priority level 1 - 010 transmit priority level 2 - 011 transmit priority level 3 - 100 transmit priority level 4 - 101 transmit priority level 5 - 110 transmit priority level 6 - 111 transmit priority level 7 (highest) bit [6]: ? fixed discard priority (default 0) - 0 - discard priority level 0 (lowest) - 1 - discard priority level 7(highest) bit [7]: ? enable fix priority (default 0) - 0 disable fix priority. al l frames are analysed. transmit priori ty and drop priority are based on vlan tag, tos or logical port. - 1 transmit priority and disca rd priority are based on va lues programmed in bit [6:3]
MVTX2801 data sheet 36 zarlink semiconductor inc. pvmap02_0,3 i 2 c address h1c, 1f; serial interface address:h10a, 10d) see above format pvmap03_0,3 i 2 c address h20,23; serial interface address:h10e, 111) see above format 10.3.5 pvmode i 2 c address: h038, serial interface address:h126 accessed by serial interface (r/w) 10.4 group 2 address - port trunking group 10.4.1 trunk0_mode - trunk group 0 and 1 mode i 2 c address: h039, serial interface address:h207 accessed by serial interface and i 2 c (r/w) port selection in unmanaged mode. trunk group 0 and trunk group 1 are enable accordingly to bit [1:0] when input pin p_d[9] = 0 (external pull down). 76543 0 mp bpdu dm reserved bit [3:0]: ? reserved - must be '0' bit [4]: ? disable mac address 0 - 0: mac address 0 is not leaned. - 1: mac address 0 is leaned. bit [5]: ? force bpdu as multicast frame (default 0) - 1: enable. bpdu frames (frames with destination mac address in the range of 01-80-c2 00-00-00 through 01-80-c2-00-00-0f) are forwarded as multicast frames. - 0: disable. drop frames in this range. bit [6]: ? mac/port - 0: single mac address per system - 1: single mac address per port bit [7]: ? reserved 7210 port sel
MVTX2801 data sheet 37 zarlink semiconductor inc. 10.4.2 tx_age - tx queue aging timer i 2 c address: h03b;serial interface address:h312 accessed by serial interface and i 2 c (r/w) 10.5 group 4 address - search engine group 10.5.1 agetime_low - mac address aging time low i 2 c address h03c; serial interface address:h400 accessed by serial interface and i 2 c (r/w) bit [7:0] low byte of the mac address aging timer. (default 2c) mac address aging is enable/disable by boot strap t_d[9]. 10.5.2 agetime_high -mac address aging time high i 2 c address h03d; serial interface address h401 accessed by serial interface and i 2 c (r/w) bit [7:0]: high byte of the mac address aging timer. (default 00) aging time is based on the following equation: {agetime_high,agetime_low} x (# of mac entries x100sec) note : the number of entries= 66k when t_d[5] is pull down (sram memory size = 512k) and 34k when t_d[5] is pull up (sram memory size = 256k). bit [1:0]: ? port member selection for trunk 0 and 1 in unmanaged mode (default 2'b00) - 00 - only trunk group 0 is enable. port 0 and 1 are used for trunk group0 - 01 - only trunk group 0 is enable. port 0,1 and 2 are used for trunk group0 - 10 - only trunk group 0 is enable. port 0,1,2 and 3 are used for trunk group0 - 11 - trunk group 0 and 1 are enable. port 0, 1 used for trunk group0, and port 2 and 3 are used for trunk group1 76 5 0 tx queue agent bit[4:0]: ? unit of 100ms (default 8). disable transmission queue aging if value is zero. bit[5]: ? must be set to '0' bit[7:6]: ? reserved
MVTX2801 data sheet 38 zarlink semiconductor inc. 10.5.3 se_opmode - search engine operation mode serial interface address:h403 accessed by cpu (r/w) 10.6 group 5 address - buffer control/qos group 10.6.1 fcbat - fcb aging timer i 2 c address h03e; serial interface address:h500 10.6.2 qosc - qos control i 2 c address h03f; serial interface address:h501 accessed by serial interface and i 2 c (r/w) 765 0 sl dms bit [5:0]: ? reserved bit [6]: ? disable mct speed-up aging (default 0) - 1 - disable speed-up aging when mct resource is low. - 0 - enable speed-up aging when mct resource is low. bit [7]: ? slow learning (default 0) - 1- enable slow learning. learning is temporary disabled when search demand is high - 0 - learning is performed independent of search demand 70 fcbat bit [7:0]: ? fcb aging time. unit of 1ms. (default ff) ? fcbat define the aging time out interval of fcb handle 76 5 43 10 to s - d to s - p v f 1 c f b bit [0]: ? qos frame lost is ok. priority will be av ailable for flow control enabled source only when this bit is set (default 0) bit [4]: ? per vlan (port based) multicast flow control (default 0) - 0 - disable -1 - enable bit [5]: ? reserved
MVTX2801 data sheet 39 zarlink semiconductor inc. 10.6.3 fcr - flooding control register i 2 c address h040; serial interface address:h502 accessed by serial interface and i 2 c (r/w) 10.6.4 avpml - vlan priority map i 2 c address h041; serial interface address:h503 accessed by serial interface and i 2 c (r/w) registers avpml, avpmm, and avpmh allow the eight vlan priorities to map into ei ght internal level transmit priorities. under the internal transmit priority, ?seven? is the highest priority where as ?zero? is the lowest. this feature allows the user the fl exibility of redefining the vlan priority field. for ex ample, programming a value of 7 into bit 2:0 of the avpml register would map packet vlan pr iority) into internal transmit priority 7. the new priority is used only inside the 2801. when the packet goes out it carries the original priority. bit [6]: ? select tos bits for priority (default 0) - 0 - use tos [4:2] bits to map the transmit priority - 1 - use tos [5:3] bits to map the transmit priority bit [7]: ? select tos bits for drop (default 0) - 0 - use tos [4:2] bits to map the drop priority - 1 - use tos [5:3] bits to map the drop priority 76 43 0 tos timebase u2mr bit [3:0]: ? u2mr: unicast to multicast rate. units in terms of time base defined in bits [6:4]. this is used to limit the amount of flooding traffic. the va lue in u2mr specifies how many packets are allowed to flood within the time specified by bi t [6:4]. to disable this function, program u2mr to 0. (default = 4'h8) bit [6:4]: ? timebase: (default = 000) - 000 = 10us - 001 = 20us - 010 = 40us - 011 = 80us - 100 = 160us - 101 = 320us - 110 = 640us - 111 = 10us, same as 000. bit [7]: ? select vlan tag or tos field (ip packets) to be preferentially picked to map transmit priority and drop priority (default = 0) . - 0 - select vlan tag priority field over tos field - 1 - select tos field over vlan tag priority field 765 32 0 vp2 vp1 vp0
MVTX2801 data sheet 40 zarlink semiconductor inc. 10.6.5 avpmm - vlan priority map i 2 c address h042, serial interface address:h504 accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 10.6.6 avpmh - vlan priority map i 2 c address h043, serial interface address:h505 accessed by serial interface and i 2 c (r/w) map vlan priority into eight level transmit priorities: 10.6.7 tospml - tos priority map i 2 c address h044, serial interface address:h506 accessed by serial interface and i 2 c (r/w) bit [2:0]: ? mapped priority of 0 (default 000) bit [5:3]: ? mapped priority of 1 (default 001) bit [7:6]: ? mapped priority of 2 (default 10) 76 43 10 vp5 vp4 vp3 vp2 bit [0]: ? mapped priority of 2 (default 0) bit [3:1]: ? mapped priority of 3 (default 011) bit [6:4]: ? mapped priority of 4 (default 100) bit [7]: ? mapped priority of 5 (default 1) 754210 vp7 vp6 vp5 bit [1:0]: ? mapped priority of 5 (default 10) bit [4:2]: ? mapped priority of 6 (default 110) bit [7:5]: ? mapped priority of 7 (default 111) 765320 tp2 tp1 tp0
MVTX2801 data sheet 41 zarlink semiconductor inc. map tos field in ip packet into four level transmit priorities 10.6.8 tospmm - tos priority map i 2 c address h045, serial interface address:h507 accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level tran smit priorities 10.6.9 tospmh - tos priority map i 2 c address h046, serial interface address:h508 accessed by serial interface and i 2 c (r/w) map tos field in ip packet into four level transmit priorities: 10.6.10 avdm - vlan discard map i 2 c address h047, serial interface address:h509 accessed by serial interface and i 2 c (r/w) bit [2:0]: ? mapped priority when tos is 0 (default 000) bit [5:3]: ? mapped priority when tos is 1 (default 001) bit [7:6]: ? mapped priority when tos is 2 (default 10) 7 6 4310 tp5 tp4 tp3 tp2 bit [0]: ? mapped priority when tos is 2 (default 0) bit [3:1]: ? mapped priority when tos is 3 (default 011) bit [6:4]: ? mapped priority when tos is 4 (default 100) bit [7]: ? mapped priority when tos is 5 (default 1) 754 21 0 tp7 tp6 tp5 bit [1:0]: ? mapped priority when tos is 5 (default 01) bit [4:2]: ? mapped priority when tos is 6 (default 110) bit [7:5]: ? mapped priority when tos is 7 (default 111) 76543210 fdv7 fdv6 fdv5 fdv4 fdv3 fdv2 fdv1 fdv0
MVTX2801 data sheet 42 zarlink semiconductor inc. map vlan priority into frame discard when low priority buffer usage is above threshold. frames with high discard (drop) priority will be disc arded (dropped) befor e frames with low drop priority. - 0 - low discard priority - 1 - high discard priority 10.6.11 tosdml - tos discard map i 2 c address h048, serial interface address:h50a accessed by serial interface and i 2 c (r/w ) map tos into frame discard when low priority buffer usage is above threshold 10.6.12 bmrc - broadcas t/multicast rate control i 2 c address h049, serial interface address:h50b accessed by serial interface and i 2 c (r/w) bit [0]: ? frame discard priority for fr ames with vlan transmit priority 0 (default 0) bit [1]: ? frame discard priority for fr ames with vlan transmit priority 1 (default 0) bit [2]: ? frame discard priority for fr ames with vlan transmit priority 2 (default 0) bit [3]: ? frame discard priority for fr ames with vlan transmit priority 3 (default 0) bit [4]: ? frame discard priority for fr ames with vlan transmit priority 4 (default 0) bit [5]: ? frame discard priority for fr ames with vlan transmit priority 5 (default 0) bit [6]: ? frame discard priority for fr ames with vlan transmit priority 6 (default 0) bit [7]: ? frame discard priority for fr ames with vlan transmit priority 7 ( default 0) 76543210 fdt7 fdt6 fdt5 fdt4 fdt3 fdt2 fdt1 fdt0 bit [0]: ? frame discard priority for frames with tos transmit priority 0 (default 0) bit [1]: ? frame discard priority for frames with tos transmit priority 1 (default 0) bit [2]: ? frame discard priority for frames with tos transmit priority 2 (default 0) bit [3]: ? frame discard priority for frames with tos transmit priority 3 (default 0) bit [4]: ? frame discard priority for frames with tos transmit priority 4 (default 0) bit [5]: ? frame discard priority for frames with tos transmit priority 5 (default 0) bit [6]: ? frame discard priority for frames with tos transmit priority 6 (default 0) bit [7]: ? frame discard priority for frames with tos transmit priority 7 (default 0) 7430 broadcast rate multicast rate
MVTX2801 data sheet 43 zarlink semiconductor inc. this broadcast and multicast rate defines for each port the number of incoming packet allowed to be forwarded within a specified time. once th e packet rate is reached, packets will be dro pped. to turn off the rate limit, program the field to 0. 10.6.13 ucc - unicast congestion control i 2 c address h04a, serial interface address:h50c accessed by serial interface and i 2 c (r/w) 10.6.14 mcc - multicast congestion control i 2 c address h0b7, serial interface address:h50d accessed by serial interface and i 2 c (r/w) 10.6.15 prg - port reservation for giga ports i 2 c address h0b9, serial interface address:h50f accessed by serial interface and i 2 c (r/w) bit [3:0]: ? multicast rate control number of multicast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) . bit [7:4]: ? broadcast rate control number of broadcast packets allowed within the time defined in bits 6 to 4 of the flooding control register (fcr). (default 0) 70 unicast congest threshold bit [7:0]: ? number of frame count. used for best ef fort dropping at b% when destination port's best effort queue reaches ucc threshold and shared pool is all in use. granularity 16 frame. (default: h07) 7 543 0 fc reaction prd multicast congest threshold bit [3:0]: ? in multiples of two. used for triggeri ng mc flow control when destination port's best effort queue reaches mcc threshold. (default 5'h08) bit [4]: ? must be 0 bit [7:5]: ? flow control reaction period. ([7:5] 4)+3 usec (default 3'h2) . 7430 buffer low thd per source buffer reservation
MVTX2801 data sheet 44 zarlink semiconductor inc. fcb reservation 10.6.16 sfcb - share fcb size i 2 c address h04e), serial interface address:h510 accessed by serial interface and i 2 c (r/w) 10.6.17 c2rs - class 2 reserved size i 2 c address h04f, serial interface address:h511 accessed by serial interface and i 2 c (r/w) bit [3:0]: ? per source buffer reservation. define the space in the fdb reserved for each port. expressed in multiples of 16 packets. for each packet 1536 bytes are reserved in the memory. default : 4'ha for 4mb memory 4'h6 for 2mb memory 4'h3 for 1mb memory bits [7:4]: ? expressed in multiples of 16 packets. threshold for dropping all best effort frames when destination port best effort queues reach ucc threshold and shared pool is all used and source port reservation is at or below the pr g[7:4] level. also the threshold for initiating uc flow control. default : 4'h6 for 4mb memory 4'h2 for 2mb memory 4'h1 for 1mb memory 70 shared buffer size bits [7:0]: ? expressed in multiples of 8. buffer reservation for shared pool. - (default 4g & 4m = 8'd62) - (default 4g & 2m = 8'd20) - (default 4g & 1m = 8'd08) - (default 8g & 4m = 8'd150) - (default 8g & 2m = 8'd55) - (default 8g & 1m = 8'd25) 70 class 2 fcb reservation bits [7:0]: ? buffer reservation for class 2 (third lowest priority). granularity 2. (default 8'h00)
MVTX2801 data sheet 45 zarlink semiconductor inc. 10.6.18 c3rs - class 3 reserved size i 2 c address h050, serial interface address:h512 accessed by serial interface and i 2 c (r/w) 10.6.19 c4rs - class 4 reserved size i 2 c address h051, serial interface address:h513 accessed by serial interface and i 2 c (r/w) 10.6.20 c5rs - class 5 reserved size i 2 c address h052; serial interface address:h514 accessed by serial interface and i 2 c (r/w) 10.6.21 c6rs - class 6 reserved size i 2 c address h053; serial interface address:h515 accessed by serial interface and i 2 c (r/w) 70 class 3 fcb reservation bits [7:0]: ? buffer reservation for class 3. granularity 2. (default 8'h00) 70 class 4 fcb reservation bits [7:0]: ? buffer reservation for class 4. granularity 2. (default 8'h00) 70 class 5 fcb reservation bits [7:0]: ? buffer reservation for class 5. granularity 2. (default 8'h00) 70 class 6 fcb reservation bits [7:0]: ? buffer reservation for class 6 (second highest priority). granularity 2. (default 8'h00)
MVTX2801 data sheet 46 zarlink semiconductor inc. 10.6.22 c7rs - class 7 reserved size i 2 c address h054; serial interface address:h516 accessed by serial interface and i 2 c (r/w) ? classes byte gigabit port 0 10.6.23 qosc00 - byte_c2_g0 i 2 c address h055, serial interface address:h517 10.6.24 qosc01 - byte_c3_g0 i 2 c address h056, serial interface address:h518 10.6.25 qosc02 - byte_c4_g0 i 2 c address h057, serial interface address:h519 10.6.26 qosc03 - byte_c5_g0 i 2 c address h058, serial interface address:h51a 70 class 7 fcb reservation bits [7:0]: ? buffer reservation for class 7 (highest priority). granularity 2. (default 8'h00) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) (1024byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) (512byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) (256byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) (128byte/unit when delay bound is used) (1024byte/unit when wfq is used)
MVTX2801 data sheet 47 zarlink semiconductor inc. 10.6.27 qosc04 - byte_c6_g0 i 2 c address h059, serial interface address:h51b 10.6.28 qosc05 - byte_c7_g0 i 2 c address h05a, serial interface address:h51c qosc00 through qosc05 represent the values f-a in ta ble 3 for gigabit port 0. they are per-queue byte thresholds for weighted random early drop (wred). qosc05 represents a, a nd qosc00 represents f. classes byte gigabit port 1 10.6.29 qosc06 - byte_c2_g1 i 2 c address h05b, serial interface address:h51d 10.6.30 qosc07 - byte_c3_g1 i 2 c address h05c, serial interface address:h51e 10.6.31 qosc08 - byte_c4_g1 i 2 c address h05d, serial interface address:h51f 10.6.32 qosc09 - byte_c5_g1 i 2 c address h05e, serial interface address:h520 bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) (64byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) (64byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) (1024byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0] ? byte count threshold for c3 queue wred (default 8'h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) (256 byte/unit when delay bound is used) (1024byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2801 data sheet 48 zarlink semiconductor inc. 10.6.33 qosc0a - byte_c6_g1 i 2 c address h05f, serial interface address:h521 10.6.34 qosc0b - byte_c7_g1 i 2 c address h060, serial interface address:h522 qosc06 through qosc0b represent the values f-a in table 3. they are per-queue byte thresholds for random early drop. qosc0b represents a, and qosc06 represents f. classes byte gigabit port 2 10.6.35 qosc0c - byte_c2_g2 i 2 c address h061, serial interface address:h523 10.6.36 qosc0d - byte_c3_g2 i 2 c address h062, serial interface address:h524 10.6.37 qosc0e - byte_c4_g2 i 2 c address h063, serial interface address:h525 bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2801 data sheet 49 zarlink semiconductor inc. 10.6.38 qosc0f - byte_c5_g2 i 2 c address h064, serial interface address:h526 10.6.39 qosc10 - byte_c6_g2 i 2 c address h065, serial interface address:h527 10.6.40 qosc11 - byte_c7_g2 i 2 c address h066, serial interface address:h528 qosc0c through qosc11 represent the values f-a in table 3 for gigabit port 2. they are per-queue byte thresholds for random early drop. qosc11 represents a, and qosc0c represents f. classes byte gigabit port 3 10.6.41 qosc12 - byte_c2_g3 i 2 c address h067, serial interface address:h529 10.6.42 qosc13 - byte_c3_g3 i 2 c address h068, serial interface address:h52a 10.6.43 qosc14 - byte_c4_g3 i 2 c address h069, serial interface address:h52b bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c2 queue wred (default 8'h28) (1024 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c3 queue wred (default 8'h28) (512 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c4 queue wred (default 8'h28) (256 byte/unit when delay bound is used) (1024 byte/unit when wfq is used)
MVTX2801 data sheet 50 zarlink semiconductor inc. 10.6.44 qosc15 - byte_c5_g3 i 2 c address h06a, serial interface address:h52c 10.6.45 qosc16 - byte_c6_g3 i 2 c address h06b, serial interface address:h52d 10.6.46 qosc17 - byte_c7_g3 i 2 c address h06c, serial interface address:h52e qosc12 through qosc17 represent the values f-a in ta ble 3 for gigabit port 3. they are per-queue byte thresholds for random early drop. qosc17 represents a, and qosc12 represents f. classes wfq credit set 0 10.6.47 qosc33 - credit_c0_g0 serial interface address:h54a see table below: bits [7:0]: ? byte count threshold for c5 queue wred (default 8'h28) (128 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c6 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [7:0]: ? byte count threshold for c7 queue wred (default 8'h50) (64 byte/unit when delay bound is used) (1024 byte/unit when wfq is used) bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: priority type. define one of the four qos mode of operation for port 0 (default 2'00) - 00: option 1 - 01: option 2 - 10: option 3 - 11: option 4 queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0
MVTX2801 data sheet 51 zarlink semiconductor inc. 10.6.48 qosc34 - credit_c1_g0 serial interface address:h54b 10.6.49 qosc35 - credit_c2_g0 serial interface address:h54c 10.6.50 qosc36 - credit_c3_g0 serial interface address:h54d 10.6.51 qosc37 - credit_c4_g0 serial interface address:h54e bits [7]: ? flow control allow during wfq scheme. (default 1'b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_status i ngress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved
MVTX2801 data sheet 52 zarlink semiconductor inc. 10.6.52 qosc38 - credit_c5_g0 serial interface address:h54f 10.6.53 qosc39- credit_c6_g0 serial interface address:h550 10.6.54 qosc3a- credit_c7_g0 serial interface address:h551 qosc33 through qosc3arepresents the set of wfq parame ters (see section 7.5) for gigabit port 0. the granularity of the numbers (bits [5:0]) is 1, and thei r sum must be 64. qosc33 corresponds to w0, and qosc3a corresponds to w7. classes wfq credit port g1 10.6.55 qosc3b - credit_c0_g1 serial interface address:h552 see table below: bits [5:0] ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: priority type. define one of t he four qos mode of operation for port 1 (default 2'00) - 00: option 1 - 01: option 2 - 10: option 3 - 11: option 4 queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0
MVTX2801 data sheet 53 zarlink semiconductor inc. 10.6.56 qosc3c - credit_c1_g1 serial interface address:h54b 10.6.57 qosc3d - credit_c2_g1 serial interface address:h553 10.6.58 qosc3e - credit_c3_g1 serial interface address:h554 10.6.59 qosc3f - credit_c4_g1 serial interface address:h555 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_s tatus ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved
MVTX2801 data sheet 54 zarlink semiconductor inc. 10.6.60 qosc40 - credit_c5_g1 serial interface address:h556 10.6.61 qosc41- credit_c6_g1 serial interface address:h557 10.6.62 qosc42- credit_c7_g1 serial interface address:h558 qosc3b through qosc42 represents the set of wfq par ameters (see section 7.5) for gigabit port 1. the granularity of the numbers (bits [5:0]) is 1, and thei r sum must be 64. qosc3b corresponds to w0, and qosc42 corresponds to w7. classes wfq credit port g2 10.6.63 qosc43 - credit_c0_g2 serial interface address:h55a see table below: bits [5:0] ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 2 (default 2'00) - 00: option 1 - 01: option 2 - 10: option 3 - 11: option 4 queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7 w6 w5 w4 w3 w2 w1 w0
MVTX2801 data sheet 55 zarlink semiconductor inc. 10.6.64 qosc44 - credit_c1_g2 serial interface address:h55b 10.6.65 qosc45 - credit_c2_g2 serial interface address:h55c 10.6.66 qosc46 - credit_c3_g2 serial interface address:h55d 10.6.67 qosc47 - credit_c4_g2 serial interface address:h55e bits [7]: ? flow control allow during wfq scheme. (default 1'b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) 0= do not send any frames if the xoff is on. 1= the p7-p2 frames can be sent even the xoff is on bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc_s tatus ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad x0 1(wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved
MVTX2801 data sheet 56 zarlink semiconductor inc. 10.6.68 qosc48 - credit_c5_g2 serial interface address:h55f 10.6.69 qosc49- credit_c6_g2 serial interface address:h560 10.6.70 qosc4a- credit_c7_g2 serial interface address:h561 qosc43 through qosc4arepresents the set of wfq parame ters (see section 7.5) for gigabit port 2. the granularity of the numbers (bits [5:0]) is 1, and thei r sum must be 64. qosc43 corresponds to w0, and qosc4a corresponds to w7. classes wfq credit port g3 10.6.71 qosc4b - credit_c0_g3 serial interface address:h562 see table below bits [5:0] ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved bits [5:0]: ? w0 - credit register for wfq. (default 6'h04) bits [7:6]: ? priority type. define one of the four qos mode of operation for port 3 (default 2'00) - 00: option 1 - 01: option 2 - 10: option 3 - 11: option 4 queue p7p6p5p4p3p2p1p0 option 1 bit [7:6] = 2'b00 delay bound be option 2 bit [7:6] = 2'b01 sp delay bound be option 3 bit [7:6] = 2'b10 sp wfq option 4 bit [7:6] = 2'b11 wfq credit for wfq - bit [5:0] w7w6w5w4w3w2w1w0
MVTX2801 data sheet 57 zarlink semiconductor inc. 10.6.72 qosc4 - credit_c1_g3 serial interface address:h563 10.6.73 qosc4d - credit_c2_g3 serial interface address:h564 10.6.74 qosc4e - credit_c3_g3 serial interface address:h565 10.6.75 qosc4f - credit_c4_g3 serial interface address:h566 bits [7]: ? flow control allow during wfq scheme. (default 1'b1) 0 = not support qos when the source port flow control status is on. 1= always support qos) bits [6]: ? flow control be queue only. (default 1'b1) (0= do not send any frames if the xoff is on. (1= the p7-p2 frames can be sent even the xoff is on) bits [5:0] ? w1 - credit register. (default 4'h04) fc_allow fc_be_only lost_ok egress- for dest fc _status ingress- for src fc status 0 0 0 go to be queue if (src fc or des fc on) otherwise normal 0 0 1 go to be queue if (dest fc on) otherwise normal 1 0 0 (wfq only) go to be queue if (src fc on) otherwise bad 1 0 1 (wfq only) always normal x 1 0 go to be queue if (src fc on) x 1 1 always normal bits [5:0] ? w2 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w3 - credit register. (default 4'h04) bits [7:6]: ? reserved bits [5:0] ? w4 - credit register. (default 4'h04) bits [7:6]: ? reserved
MVTX2801 data sheet 58 zarlink semiconductor inc. 10.6.76 qosc50 - credit_c5_g3 serial interface address:h567 10.6.77 qosc51- credit_c6_g3 serial interface address:h568 10.6.78 qosc52- credit_c7_g3 serial interface address:h569 qosc4b through qosc52 represents the set of wfq par ameters (see section 7.5) for gigabit port 3. the granularity of the numbers (bits [5:0]) is 1, and thei r sum must be 64. qosc4b corresponds to w0, and qosc52 corresponds to w7. class 6 shaper control port g0 10.6.79 qosc73 - token_rate_g0 serial interface address:h58a 10.6.80 qosc74 - token_limit_g0 serial interface address:h58b qosc73 and qosc74 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc73 is an integer less than 64, with granularity 1. qosc74 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc73 and qosc74 apply to gigabit port 0. register qosc39-credit_c6_g0 programs the peak rate. se e qos application note for more information. class 6 shaper control port g1 bits [5:0] ? w5 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w6 - credit register. (default 5'h8) bits [7:6]: ? reserved bits [5:0] ? w7 - credit register. (default 5'h10) bits [7:6]: ? reserved bits [7:0] ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0] ? bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0)
MVTX2801 data sheet 59 zarlink semiconductor inc. 10.6.81 qosc75 - token_rate_g1 serial interface address:h58c 10.6.82 qosc76 - token_limit_g1 serial interface address:h58d qosc75 and qosc76 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc75 is an integer less than 64, with granularity 1. qosc76 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc75 and qosc76 apply to gigabit port 1. register qosc41-credit_c6_g1 programs the peak rate. se e qos application note for more information. class 6 shaper control port g2 10.6.83 qosc77 - token_rate_g2 serial interface address:h58e 10.6.84 qosc78 - token_limit_g2 serial interface address:h58f qosc77 and qosc78 correspond to parameters from sect ion 7.6 on the shaper for ef traffic. qosc77 is an integer less than 64, with granularity 1. qosc78 is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc77 and qosc78 apply to gigabit port 2. register qosc49-credit_c6_g2 programs the peak rate. se e qos application note for more information. class 6 shaper control port g3 10.6.85 qosc79 - token_rate_g3 serial interface address:h590 bits [7:0] ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0] ? bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0] ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08) bits [7:0] ? bytes allow to continue trans mit out when regulated by shaper logic. (16byte/unit) (default: 8'hc0) bits [7:0] ? bytes allow to transmit every frame time (0.512usec) when regulated by shaper logic. (default: 8'h08)
MVTX2801 data sheet 60 zarlink semiconductor inc. 10.6.86 qosc7a - token_limit_g3 serial interface address:h591 qosc79 and qosc7a correspond to parameters from secti on 7.6 on the shaper for ef traffic. qosc79 is an integer less than 64, with granularity 1. qosc7a is the programmed maximum value of the counter (maximum burst size). this value is expressed in multiples of 16. qosc79 and qosc7a apply to gigabit port 3. register qosc51-credit_c6_g3 programs the peak rate. se e qos application note for more information. 10.6.87 rdrc0 - wred rate control 0 i 2 c address 085, serial interface address:h59a accessed by serial interface and i 2 c (r/w) 10.6.88 rdrc1 - wred rate control 1 i 2 c address 086, serial interface address:h59b accessed by serial interface and i 2 c (r/w) bits [7:0] ? bytes allow to to continue transmit out when regulated by shaper logic. ? (16byte/unit) (default: 8?hc0) 7430 x rate y rate bits [7:4]: ? corresponds to the percentage x% in chapter 7. used for random early drop. granularity 6.25%. (default: 4'h8) bits[3:0]: ? corresponds to the percentage y% in chapter 7. used for random early drop. granularity 6.25%. (default: 4'he) 7430 z rate b rate bits [7:4]: ? corresponds to the percentage z% in chapter 7. used for random early drop. granularity 6.25%.%. (default: 4'h6) bits[3:0]: ? corresponds to the best effort frame dr op percentage b%, when shared pool is all in use and destination port best effort queue reaches ucc. used for random early drop. granularity 6.25%.%. (default: 4'h8)
MVTX2801 data sheet 61 zarlink semiconductor inc. 10.7 group 6 address - misc group 10.7.1 mii_op0 - mii register option 0 i 2 c address h0b1, serial interface address:h600 accessed by serial interface and i 2 c (r/w) 10.7.2 mii_op1 - mii register option 1 i 2 c address 0b2, serial interface address:h601 accessed by serial interface and i 2 c (r/w) 10.7.3 fen - feature register i 2 c address h0b3, serial interface address:h602 accessed by serial interface and i 2 c (r/w) 7654 0 hfc 1prst np vendor spc. reg addr bit [7]: ? half duplex flow control no defaul t enable (do not use half duplex mode) - 0 = half duplex flow control always enable - 1 = half duplex flow control by negotiation bit[6]: ? link partner reset auto-negotiate disable bit [5] ? next page enable - 1: enable -0: disable bit[4:0]: ? vendor specified link status regi ster address (null value means don't use it) (default 00) 7430 speed bit location duplex bit location bits[3:0]: ? duplex bit location in vendor specified register bits [7:4]: ? speed bit location in vendor specified register (default 00) 765 3210 dml mii ds
MVTX2801 data sheet 62 zarlink semiconductor inc. 10.7.4 miic0 - mii command register 0 serial interface address:h603 accessed by serial interface (r/w) bit [7:0] mii data [7:0] note : before programming mii command: set fen[6], check miic3, making sure no rdy, and no valid; then program mii command. 10.7.5 miic1 - mii command register 1 serial interface address:h604 accessed by serial interface (r/w) note : before programming mii command: set fen[6], che ck miic3, making sure no rdy and no valid; then program mii command. 10.7.6 miic2 - mii command register 2 serial interface address:h605 accessed by serial interface (r/w) note : before programming mii command: set fen[6], che ck miic3, making sure no rdy and no valid; then program mii command. bits [1:0]: ? reserved bit [2]: ? support ds ef code. (default 0) - 0 - disable - 1 - enable (all ports) ? when 101110 is detected in ds field (tos[7:2]), the frame priority is set for 110 and drop is set for 0. bit [5:3]: ? reserved bit [6]: - 0: enable mii management state machine (default 0) - 1: disable mii management state machine bit [7]: - 0: enable using mct link list structure - 1: disable using mct link list structure bit [7:0] ? mii data [15:8] 7654 0 mii op register address bits [4:0]: ? reg_ad - register phy address bit [6:5] ? op - operation code ?10? for read command and ?01? for write command
MVTX2801 data sheet 63 zarlink semiconductor inc. 10.7.7 miic3 - mii command register 3 serial interface address:h606 accessed by serial interface (r/w) note : before programming mii command: set fen[6], che ck miic3, making sure no rdy and no valid; then program mii command. 10.7.8 miid0 - mii data register 0 serial interface address:h607 accessed by serial interface (ro) 10.7.9 miid1 - mii data register 0 serial interface address:h608 accessed by serial interface (ro) 10.7.10 led mode - led control i 2 c address:h0b4; serial interface address:h609 accessed by serial interface and i 2 c (r/w) 7654 0 rdy valid phy address bits [4:0]: ? phy_ad - 5 bit phy address bit [6] ? valid - data valid from phy (read only) bit [7] ? rdy - data is returned from phy (ready only) bit [7:0] ? mii data [7:0] bit [7:0] ? mii data [15:8] 765 4 3 2 1 0 lpbk out pattern clock rate hold time bit[1:0] ? sample hold time (default 2'b00) 2'b00- 8 msec 2'b01- 16 msec 2'b10- 32 msec 2'b11- 64 msec
MVTX2801 data sheet 64 zarlink semiconductor inc. bit[3:2] ? led clock speed (serial mode) (default 2'b10) 2'b00- sclk/128 2'b01- sclk/256 2'b10- sclk/1024 2'b11- sclk/2048 led clock speed (parallel mode) (default 2'b10) 2'b00- sclk/1024 2'b01- sclk/4096 2'b10- sclk/2048 2'b11- sclk/8192 bit[5:4] led indicator out pattern (default 2'b11) 2'b00- normal output, led signals go st raight out, no logical combination 2'b01- 4 bi-color led mode 2'b10- 3 bi-color led mode 2'b11- programmable mode normal mode: led_byteout_[7]:collision (col) led_byteout_[6]:full duplex (fdx) led_byteout_[5]:speed[1] (sp1) led_byteout_[4]:speed[0] (sp0) led_byteout_[3]:link (lnk) led_byteout_[2]:rx (rxd) led_byteout_[1]:tx (txd) bit[5:4] cont?d led_byteout_[0]:flow control (fc) 4 bi-color led mode led_byteout_[7]:col led_byteout_[6]:1000fdx led_byteout_[5]:1000hdx led_byteout_[4]:100fdx led_byteout_ [3]:100hdx led_byteout_[2]:10fdx led_byteout_[1]:10hdx led_byteout_[0]:act note: all output qualified by link signal 3 bi-color led mode:
MVTX2801 data sheet 65 zarlink semiconductor inc. 10.7.11 checksum - eeprom checksum i 2 c address h0c5, serial interface address:h60b accessed by serial interface and i 2 c (r/w) 10.7.12 led user 10.7.13 leduser0 i 2 c address h0bb, serial interface address:h60c accessed by serial interface and i 2 c (r/w) led_byteout_[7]:col led_byteout_[6]:lnk led_byteout_[5]:fc led_byteout_[4]:spd1000 led_byteout_[3]:spd100 led_byteout_[2]:fdx led_byteout_[1]:hdx led_byteout_[0]:act note: all output qualified by link signal programmable mode: led_byteout_[7]:link led_byteout_[6:0]:defined by the ledsig6 ~ ledsig0 programmable registers. note: all output qualified by link signal bit[6]: ? reserved. must be '0' bit[7]: ? enable internal loop back. when this bit is set to '1' all ports work in internal loop back mode. for normal operation must be '0'. bit [7:0]: ? (default 00) ? before requesting that the MVTX2801 updates the eeprom device, the correct checksum needs to be calculated and written into this checksum register. the checksum formula is: ff i 2 c register = 0 i = 0 after booting cycle the MVTX2801 calcul ates the checksum. if the checksum is not zeroed the MVTX2801 does not start. 70 led user0
MVTX2801 data sheet 66 zarlink semiconductor inc. 10.7.14 leduser1 i 2 c address h0bc, serial interface address:h60d accessed by serial interface and i 2 c (r/w) 10.7.15 leduser2/ledsig2 i 2 c address h0bd, serial interface address:h60e accessed by serial interface and i 2 c (r/w) in serial mode: in parallel mode: this register is used fo r programming the led pin - led_byteout_[2] bit [7:0]: ? (default 00) content will send out by led serial logic 70 led user1 bit [7:0]: ? (default 00) content will send out by led serial logic 70 led user2 bit [7:0]: ? (default 00) content will be sent out by led serial shift logic 7430 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4'h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h8) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_by teout_[2] = and (all selected bits)
MVTX2801 data sheet 67 zarlink semiconductor inc. 10.7.16 leduser3/ledsig3 i 2 c address:h0be, serial interface address:h60f access by cpu, serial interface (r/w) in serial mode: in parallel mode: this register is used for programming the led pin - led_byteout_[3] 10.7.17 leduser4/ledsig4 i 2 c address:h0bf, serial interface address:h610 access by cpu, serial interface (r/w) in parallel mode: this register is used fo r programming the led pin - led_byteout_[4] 70 led user3 bit [7:0]: ? (default 8'h33) content will be sent out by led serial shift logic. 7430 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0]: (default 4'h3) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h3) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_by teout_[3] = and (all selected bits) 70 led user4 bit [7:0] (default 8'h32) content will be sent out by led serial shift logic. 7430 col fdx sp1 sp0 col fdx sp1 sp0
MVTX2801 data sheet 68 zarlink semiconductor inc. 10.7.18 leduser5/ledsig5 i 2 c address:h0c0, serial interface address:h611 access by cpu, serial interface (r/w) in parallel mode: this register is used for programming the led pin - led_byteout_[5] 10.7.19 leduser6/ledsig6 i 2 c address:h0c1, serial interface address:h612 access by cpu, serial interface (r/w) bit [3:0] (default 4'h2) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h3) signal select 0: not select 1: select the corresponding bit when bits get selected, the led_by teout_[4] = and (all selected bits) 70 led user5 bit [7:0] (default 8'h20) content will be sent out by led serial shift logic. 7430 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4'h0) signal polarity: 0: not invert polarity (high true) 1: invert polarity bit [7:4] (default 4'h2) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_by teout_[5] = and (all selected bits) 70 led user6
MVTX2801 data sheet 69 zarlink semiconductor inc. in parallel mode: this register is used for programming the led pin - led_byteout_[6] 10.7.20 leduser7/ledsig1_0 i 2 c address:h0c2, serial interface address:h613 access by cpu, serial interface (r/w) in parallel mode: this register is used fo r programming the led pin - led_byteout_[2] bit [7:0] (default 8'h40) content will be sent out by led serial shift logic. 7430 col fdx sp1 sp0 col fdx sp1 sp0 bit [3:0] (default 4'b0000) signal polarity: 0: not invert pola rity (high true) 1: invert polarity bit [7:4] (default 4'b0100) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byteout_[6] = and (all selected bits), or the polarity of led_byteout_[6] is controlled by ledsig1_0[3] 70 led user7 bit [7:0] (default 8'h61) content will be sent out by led serial shift logic. 7430 gp rx tx fc p6 rx tx fc bit [7] (default 1'b0) global output polarity: this bit controls the output polarity of all led_byteout_ and led_port_sel pins. 0: no invert polarity - (led_byteout_[7:0] are high activated, led_port_sel[9:0] are low acti- vated) 1: invert polarity - (led_byteout_[7:0] are lo w activated, led_port_sel[9:0] are high activated) bit [6:4] (default 3'b110) signal select 0: not select 1: select the corresponding bit when bits get selected, the led_byt eout_[6] = or (all selected bits)
MVTX2801 data sheet 70 zarlink semiconductor inc. 10.7.21 miinp0 - mii next page data register 0 i 2 c address:h0c3, serial interface address:h614 access by cpu and serial interface only (r/w) 10.7.22 miinp1 - mii next page data register 1 i 2 c address:h0c4, serial interface address:h615 access by cpu and serial interface only (r/w) 10.8 group f address - cpu access group 10.8.1 gcr-global control register serial interface address: hf00 accessed by serial interface. (r/w) bit[3] (default 1'b0) polarity control of led_byteout_[6] 0: not invert 1: invert bit [2:0] (default 3'b001) signal select: 0: not select 1: select the corresponding bit when bits get selected, the led_byt eout_[0] = or (all selected bits) bit [7:0] mii next page data [7:0] bit [7:0] mii next page data [15:8] 743210 reset bist sr sc bit [0]: ? store configuration (default = 0) ? write '1' followed by '0' to store configuration into external eeprom bit[1]: ? store configuration and reset (default = 0) ? write '1' to store configuration into external eeprom and reset chip bit[2]: ? start bist (default = 0) ? write '1' followed by '0' to start the device's built-in self-test. the result is found in the dcr register. bit[3]: ? soft reset (default = 0) ? write '1' to reset the chip bit[7:4]: ? reserved
MVTX2801 data sheet 71 zarlink semiconductor inc. 10.8.2 dcr-device stat us and signature register serial interface address: hf01 accessed by serial interface. (ro) 10.8.3 dcr01-giga port status serial interface address: hf02 accessed by serial interface. (ro) 76543210 revision signature re binp br bw bit [0]: 1 - busy writin g configuration to i 2 c 0 - not busy writing configuration to i 2 c bit[1]: 1 - busy reading configuration from i 2 c 0 - not busy reading configuration from i 2 c bit[2]: 1 - bist in progress 0 - bist not running bit[3]: 1 - ram error 0 - ram ok bit[5:4]: device signature 00 - 4 ports device, non-management mode 01 - 8 ports device, non-management mode 10 - 4 ports device, management mode possible (need to install cpu) 11 - 8 ports device, management mo de possible (need to install cpu) bit [7:6]: revision 76 43210 cic giga1 giga0 bit [1:0]: giga port 0 strap option 00 - 100mb mii mode 01 - invalid 10 - gmii 11 - pcs bit[3:2] giga port 1 strap option 00 - 100mb mii mode 01 - invalid 10 - gmii 11 - pcs bit [7] chip initialization completed note : dcr01[7], dcr23[7], dcr45[7] and d cr67[7] have the same function.
MVTX2801 data sheet 72 zarlink semiconductor inc. 10.8.4 dcr23-giga port status serial interface address: hf03 accessed by cpu and serial interface. (ro) 10.8.5 dpst - device port status register serial interface address:hf06 accessed by cpu and serial interface (r/w) 10.8.6 dtst - data read back register serial interface address: hf07 accessed by cpu and serial interface (ro) this register provides various internal information as selected in dpst bit[2:0] 76 43210 cic giga3 giga2 bit [1:0]: giga port 2 strap option 00 - 100mb mii mode 01 - invalid 10 - gmii 11 - pcs bit[3:2] giga port 3 strap option 00 - 100mb mii mode 01 - invalid 10 - gmii 11 - pcs bit [7] chip initia lization completed bit[2:0]: read back index register. this is used for selecting what to read back from dtst. (default 00) 3'b000 - port 0 operating mode and negotiation status 3'b001 - port 1 operating mode and negotiation status 3'b010 - port 2 operating mode and negotiation status 3'b011 - port 3 operating mode and negotiation status 3'b1xx - reserved 76 5 4321 0 md infodet sigdet giga inkdn fe fdpx fc_en bit[0]: flow control enabled bit[1]: full duplex port
MVTX2801 data sheet 73 zarlink semiconductor inc. bit[2]: fast ethernet port (if not giga) bit[3]: link is down bit[4]: giga port bit[5]: signal detect (when pcs interface mode) bit[6]: pipe signal detected (pipe mode only) bit[7]: module detected (for hot swap purpose)
MVTX2801 data sheet 74 zarlink semiconductor inc. 11.0 bga and ba ll signal description 11.1 bga views (top view) figure 5 - bga diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a avdd nc9 scan_en nc nc nc nc nc nc nc nc nc nc nc nc s_clk nc nc nc nc nc b_a[16] b_a[12] b_a[7] b_a[2] b_oe# b_d[27] b_d[26] nc4 nc3 b dev_cf[ 0] la_d[0] nc7 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc b_a[17] b_a[13] b_a[8] b_a[3] b_we# b_d[30] dev_cfg [1] nc5 b_d[25] c la_d[1] la_clk la_d[3] nc6 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc b_a[18] b_a[14] b_a[11] b_a[5] b_a[4] b_d[28] avdd b_clk b_d[22] d la_d[2] la_d[5] la_d[9] nc8 nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc b_a[9] b_a[10] b_adsc# nc2 b_d[29] b_d[24] b_d[18] b_d[21] e la_d[8] la_d[7] la_d[6] la_d[4] agnd nc nc nc nc nc nc nc nc nc nc nc nc nc nc nc lb_a[20] b_a[15] b_a[6] b_d[31] agnd b_d[17] b_d[23] b_d[19] b_d[16] b_d[14] f la_d[10] la_d[11] la_d[12] la_d[13] la_d[14] vss vss vdd vdd vcc vcc vcc vss vss vcc vcc vcc vdd vdd vss vss nc1 b_d[9] b_d[10] b_d[11] b_d[12] g la_d[15] la_d[16] la_d[19] la_d[18] la_d[17] vdd vdd b_d[20] b_d[4] b_d[3] b_d[6] b_d[7] h la_d[20] la_d[21] la_d[22] la_d[29] la_d[24] b_d[15] b_d[8] p_int# b_d[1] b_d[2] j la_d[23] la_d[25] la_d[26] la_d[27] la_d[31] vdd vdd b_d[13] p_a[1] p_a[2] p_we# p_rd# k la_d[28] la_d[30] la_cs0# la_d[37] la_d[33] vdd vdd b_d[5] p_d[15] p_d[11] p_d[12] p_d[13] l la_cs1# la_rw# la_d[32] la_d[46] la_d[41] p_cs# p_d[14] p_d[7] p_d[8] p_d[10] m la_d[34] la_d[35] la_d[36] la_d[53] la_d[48] vcc vcc p_a[0] b_d[0] p_d[3] p_d[4] p_d[5] n la_d[38] la_d[40] la_d[42] la_d[61] la_d[56] vcc vss vss vss vss vss vss vcc p_d[6] p_d[9] p_d[0] p_d[1] p_d[2] p la_d[43] la_d[44] la_d[45] la_a[4] la_d[39] vcc vss vss vss vss vss vss vcc t_d[15] t_d[11] t_d[12] t_d[13] t_d[14] r la_d[49] la_d[50] la_d[51] la_d[52] la_d[47] vss vss vss vss vss vss vss vss t_d[10] t_d[5] t_d[7] t_d[8] t_d[9] t la_d[58] la_d[57] la_d[55] la_d[54] la_a[7] vss vss vss vss vss vss vss vss t_d[6] t_d[4] t_d[2] t_d[1] t_d[0] u la_d[63] la_d[62] la_d[60] la_d[59] la_a[11] vcc vss vss vss vss vss vss vcc s_rst# t_d[3] tmode[1] tmode[0] resout# v la_a[6] la_a[5] la_a[3] la_a[14] la_a[18] vcc vss vss vss vss vss vss vcc nc[7] g7_rx_e r lesyno# le_clk0 le_do w la_a[10] la_a[9] la_a[8] la_a[20] g0_txd[ 1] vcc vcc nc[3] nc[1] g7_rx_d v nc[6] nc[5] y la_a[15] la_a[13] la_a[12] g0_crs/ l g0_txd[4 ] nc[6] g7_tx_e n nc[4] nc[2] nc[0] aa la_a[19] la_a[17] la_a[16] grefc[0] g0_txd[ 7] vdd vdd nc[0] nc[3] g7_col g7_rxcl k miitxck[ 7] ab miitxck[ 0] g0_txd[2 ] g0_txd[0 ] g0_txcl k g0_tx_e r vdd vdd nc[7] g7_tx_e r nc[7] nc[5] nc[4] ac g0_rxcl k g0_txd[5 ] g0_txd[3 ] g0_rxd[ 2] g0_rxd[ 6] nc[2] nc[4] nc[2] nc[1] g7_crs/ l ad g0_rxd[ 0] g0_tx_e n g0_col g0_txd[6 ] g0_rx_d v vss vdd nc[0] nc g7_txcl k nc nc ae g0_rxd[ 5] g0_rxd[ 4] g0_rxd[ 3] g0_rxd[ 1] g1_txd[ 0] vss vdd vdd vdd vcc vcc vcc vss vss vcc vcc vcc vdd vdd vss vss nc[7] nc[6] nc[5] nc[3] nc[1] af g0_rxd[ 7] g0_rx_e r grefc[1] g1_rxd[ 2] g1_rxd[ 5] g1_rxd[ 7] g2_txd[0 ] g2_txd[7 ] g2_rxd[ 2] g2_rxd[ 4] g2_rxd[ 5] g3_txd[1 ] g3_txd[6 ] g3_col g3_rxd[ 3] g3_rxd[ 6] ind_cm g3_rxd[ 4] g3_rx_e r nc[3] nc[1] nc[4] nc[2] nc[4] nc nc[5] nc nc[6] nc nc ag g1_txd[1 ] g1_txcl k g1crs/l g1_txd[7 ] g2_txcl k g1_rxd[ 4] g2_txd[4 ] g2_txd[3 ] g2_rxd[ 3] g2_rxcl k g2_rxd[ 7] g2_rx_e r g3_tx_e n g3_rxd[ 0] g3_rxd[ 5] g3_rxd[ 7] nc m_mdio nc[1] nc[5] nc[6] nc[7] nc nc[5] miitxck[ 5] nc[1] nc[3] nc[4] nc nc[5] ah g1_txd[2 ] g1_txd[3 ] miitxck[ 1] g1_rxd[ 0] g1_rxcl k g2crs/l miitxck[ 2] g2_tx_e n g2_rxd[ 1] g2_rx_d v g3_txcl k g3_txd[3 ] g3_txd[5 ] g3_rxcl k g3_rxd[ 2] g3_rx_d v nc nc[4] nc[6] nc nc nc nc nc[3] nc nc[3] nc[6] nc[1] nc[2] nc aj g1_txd[5 ] g1_txd[4 ] g1_tx_e r g1_col g1_rxd[ 6] grefc[2] g2_txd[2 ] g2_txd[6 ] g2_rxd[ 0] g2_rxd[ 6] grefc[3] g3_txd[2 ] miitxck[ 3] g3_tx_e r g3_rxd[ 1] m_mdc nc[0] nc[5] nc[7] nc[0] nc nc nc[0] nc[6] nc[0] nc nc[4] nc nc nc[0] ak g1_txd[6 ] g1_tx_e n g1_rxd[ 1] g1_rxd[ 3] g1_rx_d v g1_rx_e r g2_txd[1 ] g2_txd[5 ] g2_tx_e r g2_col g3_crs/ l g3_txd[0 ] g3_txd[4 ] g3_txd[7 ] cm_clk g4crs/l nc[2] miitxck[ 4] nc nc[2] nc[3] nc nc[1] nc[7] nc[2] nc nc[7] nc miitxck[ 6] nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
MVTX2801 data sheet 75 zarlink semiconductor inc. 11.2 ball- signal descriptions all pins are cmos type; all input pins are 5 volt tolerance, and all output pins are 3.3 cmos drive. ball no(s) symbol i/o description l30 trunk0_en i/o - ts with pull up trunk enable external pull up or unconnected- disable trunk group 0 and 1 external pull down - enable trunk group 0 and 1 see register trunk0_mode for port selection and trunk enable. n27 trunk1_en i/o - ts with pull up trunk enable external pull up or unconnected - disable trunk group 2 and 3 external pull down - enable trunk group 2 and 3 see register trunk1_mode for port selection and trunk enable. l29, l28, n26, m30, m29, m28, n30, n29, n28 p_d[8:0] i/o - ts with pull up bootstrap function - see bootstrap section k27, l27, k30, k29, k28, j28, h28 reserved not used - leave unconnected i 2 c interface (0) note: in unmanaged mode, use i 2 c and serial control interface to configure the system j27 scl output i 2 c data clock m26 sda i/o-ts with pull up i 2 c data i/o serial control interface j29 ps_strobe input wi th weak internal pull up serial strobe pin j30 ps_di input with weak internal pull up serial data input l26 ps_do (autofd) outp ut with pull up serial data output (autofd) frame buffer interface u1, u2, n4, u3, u4, t1, t2, n5, t3, t4, m4, r4, r3, r2, r1, m5, r5, l4, p3, p2, p1, n3, l5, n2, p5, n1, k4, m3, m2, m1, k5, l3, j5, k2, h4, k1, j4, j3, j2, h5, j1, h3, h2, h1, g3, g4, g5, g2, g1, f5, f4, f3, f2, f1, d3, e1, e2, e3, d2., e4, c3, d1, c1, b2 la_d[63:0] i/o-ts with pull up frame bank a- data bit [63:0] table 8 - ball- signal descriptions
MVTX2801 data sheet 76 zarlink semiconductor inc. aa1, v5, aa2, aa3, y1, v4, y2, y3, u5, w1, w2, w3, t5, v1, v2, p4, v3 la_a[19:3] output frame bank a - address bit [19:3] w4 la_a[20] output with pull up frame bank a - address bit [20] c2 la_clk output frame bank a clock input k3 la_cs0# output with pull up frame bank a low portion chip selection l1 la_cs1# output with pull up frame bank a high portion chip selection l2 la_rw# output with pull up frame bank a read/write d18, b18, c18, a17, e17, b17, c17, e16, d17, b16, e15, c16, d16, d15, e14, c15, b15, e13, a15, d14, c14, d13, b14, a14, c13, e12, b13, a13, d12, c12, b12, a12, a11, e10, c10, b10, e9, a10, d11, d10, d8, d9, c9, b9, a9, c8, b8, a8, c7, e7, d7, b7, e8, a7, d6, c6, e6, b6, a6, a5, b5, c5, b4,a4 nc i/o-ts with pull up. no connect d22, d20, e20, d21, a21, d19, b21, c21, a20, b20, e19, c20, a19, b19, e18, c19, a18 nc output f lb_a[20] output with pull up bootstrap pin d5 nc output b11 nc output with pull up e11 nc output with pull up c11 nc output with pull up switch database interface e24,b27, d27, c27, a27, a28, b30, d28, e27, c30, d30, g26, e28, d29, e26, e29, h26, e30, j26, f30, f29, f28, f27, h27, g30, g29, k26, g27, g28, h30, h29, m27 b_d[31:0] i/o-ts with pull up switch database domain - data bit [31:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 77 zarlink semiconductor inc. c22, b22, a22, e22, c23, b23, a23, c24, d24, d23, b24, a24, e23, c25, c26, b25, a25 b_a[18:2] output switch da tabase address (512k) - address bit [18:2] c29 b_clk output switch database clock input d25 b_adsc# output with pull up swit ch database address status control b26 b_we# output with pull up switch database write chip select a26 b_oe# output with pu ll up switch database read chip select mii management interface aj16 m_mdc output mii management data clock - (common for all mii ports [3:0]) ag18 m_mdio i/o-ts with pull up mii management data i/o - (common for all mii ports -[3:0])) 2.5mhz gmii / mii interface (193) gigabit ethernet access port aj11, aj6, af3,aa4 gref_clk [3:0] input w/ pull up gigabit reference clock ad29, ak30, aj22, ag17 nc ak15 cm_clk input w/ pull up common clock shared by port g[3:0] af17 ind/cm input w/ pull up 1: select gref_clk[3:0] as clock 0: select cm_clk as clock for all ports aj13, ah7, ah3, ab1 mii tx clk[3:0] input w/ pull up aa30, ak29, ag25, ak18, nc ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[3:0] port - receive data bit [7:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 78 zarlink semiconductor inc. v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 nc ah16, ah10, ak5, ad5 g[3:0]_rx_dv input w/ pull down g[ 3:0]port - receive data valid w28, ad30, ak28, ah22, af19, ag12, ak6, af2 g[3:0]_rx_er input w/ pull up g[3:0]port - receive error v27, ad27, aj28, ah23, nc ak11, ah6, ag3, y4 g[3:0]_crs/link input w/ pull down g[3:0]port - carrier sense ac30, aj29, ag23, ak16, nc af14, ak10, aj4, ad3 g[3:0]_col input w/ pull up g[3: 0]port - collision detected aa28, af29, aj26, aj21, nc ah14, ag10, ah5, ac1 g[3:0]_rxclk input w/ pull up g[3:0]port - receive clock aa29, af27, ak26, ah21, nc ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[3:0]port - transmit data bit [7:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 79 zarlink semiconductor inc. ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 nc ag13, ah8, ak2, ad2 g[3:0]_tx_en output w/ pull up g[ 3:0]port - transmit data enable y27, ag29, ah25, ak19, nc aj14, ak9, aj3, ab5 g[3:0]_tx_er output w/ pull up g[3:0]port - transmit error ab27, af30, af25, ah20, nc ah11, ag5, ag2, ab4 g[3:0]_ txclk output g[3:0]port - gigabit transmit clock ad28, ah30, ak22, ah17, nc pma interface (193) gigabit ethernet access port (pcs) aj11, aj6, af3,aa4 gref_clk [3:0] input w/ pull up gigabit reference clock ad29, ak30, aj22, ag17, nc ak15 cm_clk input w/ pull up common clock shared by port g[3:0] af17 ind/cm input w/ pull up 1: select gref_clk[3:0] as clock 0: select cm_clk as clock for all port ag16, af16, ag15, af18, af15, ah15, aj15, ag14 ag11, aj10, af11, af10, ag9, af9, ah9, aj9 af6, aj5, af5, ag6, ak4, af4, ak3, ah4 af1, ac5, ae1, ae2, ae3, ac4, ae4, ad1 g3_rxd[7:0] g2_rxd[7:0] g1_rxd[7:0] g0_rxd[7:0] input w/ pull up g[3:0]port - pma receive data bit [7:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 80 zarlink semiconductor inc. v26, w29, w30, y28, w26, y29, w27, y30 ab26, ae27, ae28, ac27, ae29, ac26, ae30, ad26 ak27, ah27, af26, aj27, ah26, ak25, ag26, aj25 ag22, ag21, ag20, af22, ak21, ak20, af21, aj20 nc ah16, ah10, ak5, ad5 g[3:0]_rx_d[8] input w/ pull down g[3: 0]port - pma rece ive data bit [8] w28, ad30, ak28, ah22, nc af19, ag12, ak6, af2 g[3:0]_rx_d[9] input w/ pull up g[3:0]port - pma receive data bit [9] v27, ad27, aj28, ah23, nc af14, ak10, aj4, ad3 g[3:0]_rxclk1 input w/ pull up g[ 3:0]port - pma receive clock 1 aa28, af29, aj26, aj21, nc ah14, ag10, ah5, ac1 g[3:0]_rxclk0 input w/ pull up g[ 3:0]port - pma receive clock 0 aa29, af27, ak26, ah21, nc ak14, af13, ah13, ak13, ah12, aj12, af12, ak12 af8, aj8, ak8, ag7, ag8, aj7, ak7, af7 ag4, ak1, aj1, aj2, ah2, ah1, ag1, ae5 aa5, ad4, ac2, y5, ac3, ab2, w5, ab3 g3_txd[7:0] g2_txd[7:0] g1_txd[7:0] g0_txd[7:0] output g[3:0]port - pma transmit data bit [7:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 81 zarlink semiconductor inc. ab28, y26, ab29, ab30, aa27, ac28, ac29, aa26 ae26, af28, ag30, ag28, ag27, ah29, ah28, aj30 ak24, aj24, ag24, af24, ah24, af23, ak23, aj23 aj19, ah19, aj18, ah18, af20, ak17, ag19, aj17 nc ag13, ah8, ak2, ad2 g[3:0]_txd[8] output w/ pull up g[3:0]port - pma transmit data bit [8] y27, ag29, ah25, ak19, nc aj14, ak9, aj3, ab5 g[3:0]_tx_d[9] output w/ pu ll up g[3:0]port - pma transmit data bit [9] ab27, af30, af25, ah20, nc ah11, ag5, ag2, ab4 g[3:0]_ txclk output g[3:0]port - pma gigabit transmit clock ad28, ah30, ak22, ah17, nc test facility (3) u29 t_mode0 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode use external pull up for normal operation u28 t_mode1 i/o-ts with pull up test - set upon reset, and provides nand tree test output during test mode. use external pull up for normal operation a3 scan_en input with pull down enable test mode for normal operation leave it unconnected led interface (ser ial and parallel) r28, t26, r27, t27, u27, t28, t29, t30 t_d[7:0]/ led_pd[7:0] output while resetting, t_d[7,0] are in input mode and are used as strapping pins. internal pull up led_pd - parallel led data [7:0] ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 82 zarlink semiconductor inc. p27, r26, r30, r29 t_d[11:8]/ led_pt[3:0] output while resetting, t_d[11:8] are in input mode and are used as strapping pins. internal pull up led_pr[3:0] - parallel led port selection [3:0] p26, p30, p29, p28, t_d[15:12]/ led_pt[7:4] output while resetting, t_d[15:12] are in input mode and are used as strapping pins. internal pull up led_pr[7:4] - no meaning v29 led_clk0/ led_pt[8] output led_clk0 - le d serial interface output clock led_pt[8] - parallel led port sel [8] v30 led_blink/ led_do/ led_pt[9] output while resetting, le d-blink is in input mode and is used as strapping pin. 1: no blink, 0: blink. internal pull up. led_do - led serial data output stream led_pt[9] - parallel led port sel [9] v28 led_pm/ led_synco# output with pull up wh ile resetting, led_pm is in input mode and is used as strapping pin. internal pull up. 1: enable parallel interface, 0: enable serial interface. led_synco# - led output data stream envelop system clock, power, and ground pins a16 s_clk input system clock at 133 mhz u26 s_rst# input - st reset input u30 resout# output reset phy b1 dev_cfg[0] input w/ pull down not used b28 dev_cfg[1] input w/ pull down not used ae7, ae9, f10, f21, f22, f9, g25, g6, j25, j6, k25, k6, aa25, aa6, ab25, ab6, ad25, ae10, ae21, ae22 vdd power core +2.5 volt dc supply ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 83 zarlink semiconductor inc. v14, v15, v16, v17, v18, f16, f24, f25, f6, f7, n13, n14, n15, n16, n17, n18, p13, p14, p15, p16, p17, p18, r13, r14, r15, r16, r17, r18, r25, r6, t13, t14, t15, t16, t17, t18, t25, t6, u13, u14, u15, u16, u17, u18, v13, ad6, ae15, ae16, ae24, ae25, ae6, f15 vss ground ground a1, c28 avdd power analog +2.5 volt dc supply e5, e25 avss ground analog ground ae12, ae13, ae14, ae17, ae18, ae19, f12, f13, f14, f17, f18, f19, m25, m6, n25, n6, p25, p6, u25, u6, v25, v6, w25, w6 vdd power i/o +3.3 volt dc supply bootstrap pins (default= pull up, 1= pull up 0= pull down) ad2, ab5 g0_tx_en, g0_tx_er default: pcs giga0 mode: g0_txen g0_txer 0 0 mii 0 1 invalid 1 0 gmii 1 1 pcs ak2, aj3 g1_tx_en, g1_txer default: pcs giga1 mode: g1_txen g1_txer 0 0 mii 0 1 invalid 1 0 gmii 1 1 pcs ah8, ak9 g2_tx_en, g2_tx_er default: pcs giga2 mode: g0_txen g0_txer 0 0 mii 0 1 invalid 1 0 gmii 1 1 pcs ag13.aj14 g3_tx_en, g3_tx_er default: pcs giga3 mode: g0_txen g0_txer 0 0 mii 0 1 invalid 1 0 gmii 1 1 pcs after reset t_d[15:0] are used by the led interface ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 84 zarlink semiconductor inc. t30 t_d[0] 1 giga link active status 0 - active low 1 - active high t29 t_d[1] 1 power saving 0 - no power saving 1 - power saving stop mac clock if no mac activity. t28 t_d[2] must be pulled-down reserved - must be pulled-down u27 t_d[3] 1 hot plug port module detection enable 0 - module detection enable 1 - module detection disable t27 t_d[4] must be pulled-down reserved - must be pulled-down r27 t_d[5] 1 sram memory size 0 - 512k sram 1 - 256k sram t26 t_d[6] reserved r28 t_d[7] 1 fdb memory depth 1- one memory layer 0 - two memory layers w4, e21 la_a[20], lb_a[20] 11 fdb memory size 11 - 2m per bank = 4m total 10 - 1m per bank = 2m total 0x - 512k per bank = 1m total r29 t_d[8] 1 eeprom installed 0 - eeprom is installed 1 - eeprom is not installed r30 t_d[9] 1 mct aging enable 0 - mct aging disable 1 - mct aging enable r26 t_d[10] 1 fcb handle aging enable 0 - fcb handle aging disable 1 - fcb handle aging enable p27 t_d[11] 1 timeout reset enable 0 - timeout reset disable 1 - timeout reset enable issue reset if any state machine did not go back to idle for 5sec. p28, 29, 30 t_d[14:12] reserved p26 t_d[15] 1 external ram test 0 - perform the infinite loop of zbt ram bist. debug test only 1 - regular operation. ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 85 zarlink semiconductor inc. n30, n29, n28 p_d[2:0] 111 zbt ram la_clk turning 3'b000 - control by reg. lclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - use this method m30, m29, m28 p_d[5:3] 111 no use l29, l28, n26 p_d[8:6] 111 sbram b_clk turning3'b000 - control by bclkcr[2:0] 3'b001 - delay by method # 0 3'b010 - delay by method # 1 3'b011 - delay by method # 2 3'b100 - delay by method # 3 3'b101 - delay by method # 4 3'b110 - delay by method # 5 3'b111 - delay by method # 6 - use this method notes: # = active low signal input = input signal in-st = input signal with schmitt-trigger output = output signal (tri-state driver) out-od= output signal with open-drain driver i/o-ts = input & output signal with tri-state driver i/o-od = input & output signal with open-drain driver ball no(s) symbol i/o description table 8 - ball- signal descriptions (continued)
MVTX2801 data sheet 86 zarlink semiconductor inc. 11.3 ball signal name ball no. signal name ball no. signal name ball no. signal name a1 avdd m1 la_d[34] y2 la_a[13] b1 dev_cfg[0] m2 la_d[35] v4 la_a[14] b2 la_d[0] m3 la_d[36] y1 la_a[15] c2 la_clk k4 la_d[37] aa3 la_a[16] c1 la_d[1] n1 la_d[38] aa2 la_a[17] d1 la_d[2] p5 la_d[39] v5 la_a[18] c3 la_d[3] n2 la_d[40] aa1 la_a[19] e4 la_d[4] l5 la_d[41] w4 la_a[20] d2 la_d[5] n3 la_d[42] y4 g0_crs/link e3 la_d[6] p1 la_d[43] aa4 gref_clk[0] e2 la_d[7] p2 la_d[44] ab4 g0_txclk e1 la_d[8] p3 la_d[45] ab3 g0_txd[0] d3 la_d[9] l4 la_d[46] w5 g0_txd[1] f1 la_d[10] r5 la_d[47] ab2 g0_txd[2] f2 la_d[11] m5 la_d[48] ab1 mii_tx_clk[0] f3 la_d[12] r1 la_d[49] ac3 g0_txd[3] f4 la_d[13] r2 la_d[50] y5 g0_txd[4] f5 la_d[14] r3 la_d[51] ac2 g0_txd[5] g1 la_d[15] r4 la_d[52] ac1 g0_rxclk g2 la_d[16] m4 la_d[53] ad3 g0_col g5 la_d[17] t4 la_d[54] ad4 g0_txd[6] g4 la_d[18] t3 la_d[55] aa5 g0_txd[7] g3 la_d[19] n5 la_d[56] ad2 g0_tx_en h1 la_d[20] t2 la_d[57] ab5 g0_tx_er h2 la_d[21] t1 la_d[58] ad1 g0_rxd[0] h3 la_d[22] u4 la_d[59] ae4 g0_rxd[1] j1 la_d[23] u3 la_d[60] ac4 g0_rxd[2] h5 la_d[24] n4 la_d[61] ae3 g0_rxd[3] j2 la_d[25] u2 la_d[62] ae2 g0_rxd[4] table 9 - ball signal name
MVTX2801 data sheet 87 zarlink semiconductor inc. j3 la_d[26] u1 la_d[63] ae1 g0_rxd[5] j4 la_d[27] v3 la_a[3] ac5 g0_rxd[6] k1 la_d[28] p4 la_a[4] af1 g0_rxd[7] h4 la_d[29] v2 la_a[5] ad5 g0_rx_dv k2 la_d[30] v1 la_a[6] af2 g0_rx_er j5 la_d[31] t5 la_a[7] af3 gref_clk[1] k3 la_cs0# w3 la_a[8] ag2 g1_txclk l1 la_cs1# w2 la_a[9] ag3 g1_crs/link l2 la_rw# w1 la_a[10] ae5 g1_txd[0] l3 la_d[32] u5 la_a[11] ag1 g1_txd[1] k5 la_d[33] y3 la_a[12] ah1 g1_txd[2] ah2 g1_txd[3] ag10 g2_rxclk ag19 nc aj2 g1_txd[4] ak10 g2_col ak17 nc aj1 g1_txd[5] aj10 g2_rxd[6] af20 nc ak1 g1_txd[6] ag11 g2_rxd[7] ah18 nc ag4 g1_txd[7] ah10 g2_rx_dv aj18 nc ak2 g1_tx_en ag12 g2_rx_er ak18 nc ah3 mii_tx_clk[1] ak1 1 g3_crs/link ah19 nc aj3 g1_tx_er aj11 gref_clk[3] aj19 nc ah4 g1_rxd[0] ah11 g3_txclk ak19 nc ak3 g1_rxd[1] ak12 g3_txd[0] ah20 nc af4 g1_rxd[2] af12 g3_txd[1] aj20 nc ak4 g1_rxd[3] aj12 g3_txd[2] af21 nc ah5 g1_rxclk ah12 g3_txd[3] ak20 nc aj4 g1_col ak13 g3_txd[4] ah21 nc ag6 g1_rxd[4] aj13 mii_tx_clk[3] aj21 nc af5 g1_rxd[5] ah13 g3_txd[5] ak21 nc aj5 g1_rxd[6] af13 g3_txd[6] af22 nc af6 g1_rxd[7] ak14 g3_txd[7] ag20 nc ak5 g1_rx_dv ag13 g3_tx_en ag21 nc ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 88 zarlink semiconductor inc. ak6 g1_rx_er aj14 g3_tx_er ag22 nc aj6 gref_clk[2] ah14 g3_rxclk ah22 nc ag5 g2_txclk af14 g3_col aj22 nc ah6 g2_crs/link ag14 g3_rxd[0] ak22 nc af7 g2_txd[0] ak15 cm_clk ah23 nc ak7 g2_txd[1] af17 ind_cm ag23 nc aj7 g2_txd[2] aj15 g3_rxd[1] aj23 nc ag8 g2_txd[3] ah15 g3_rxd[2] ak23 nc ag7 g2_txd[4] af15 g3_rxd[3] af23 nc ah7 mii_tx_clk[2] af18 g3_rxd[4] ah24 nc ak8 g2_txd[5] ag15 g3_rxd[5] af24 nc aj8 g2_txd[6] af16 g3_rxd[6] ag24 nc af8 g2_txd[7] ag16 g3_rxd[7] aj24 nc ah8 g2_tx_en ah16 g3_rx_dv ak24 nc ak9 g2_tx_er af19 g3_rx_er ag25 nc aj9 g2_rxd[0] aj16 m_mdc ah25 nc ah9 g2_rxd[1] ag18 m_mdio af25 nc af9 g2_rxd[2] ak16 nc aj25 nc ag9 g2_rxd[3] ag17 nc ag26 nc af10 g2_rxd[4] ah17 nc ak25 nc af11 g2_rxd[5] aj17 nc ak26 nc aj26 nc aa27 nc p29 t_d[13] ah26 nc ab30 nc p30 t_d[14] aj27 nc ab29 nc p26 t_d[15] af26 nc y26 nc n28 p_d[0] ah27 nc ab28 nc n29 p_d[1] ak27 nc y27 nc n30 p_d[2] ak28 nc ab27 nc m28 p_d[3] aj28 nc aa30 nc m29 p_d[4] aj29 nc aa29 nc m30 p_d[5] ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 89 zarlink semiconductor inc. ak29 nc aa28 nc n26 p_d[6] ak30 nc y30 nc l28 p_d[7] aj30 nc w27 nc l29 p_d[8] ah28 nc y29 nc n27 trunk1_en ah29 nc w26 nc l30 trunk0_en ag27 nc y28 nc k28 nc ag28 nc w30 nc k29 nc ah30 nc w29 nc k30 nc ag30 nc v26 nc l27 nc af28 nc w28 nc k27 nc ae26 nc v27 nc m26 sda ag29 nc v30 led_do j27 scl af27 nc v29 led_clk0 j28 nc af29 nc v28 led_synco# j29 ps_strobe af30 nc u26 s_rst# j30 ps_di ad26 nc u30 resout# l26 ps_do ae30 nc u29 t_mode[0] h28 nc ac26 nc u28 t_mode[1] m27 b_d[0] ae29 nc t30 t_d[0] h29 b_d[1] ac27 nc t29 t_d[1] h30 b_d[2] ae28 nc t28 t_d[2] g28 b_d[3] ae27 nc u27 t_d[3] g27 b_d[4] ab26 nc t27 t_d[4] k26 b_d[5] ad30 nc r27 t_d[5] g29 b_d[6] ad29 nc t26 t_d[6] g30 b_d[7] ad27 nc r28 t_d[7] h27 b_d[8] ad28 nc r29 t_d[8] f27 b_d[9] ac30 nc r30 t_d[9] f28 b_d[10] aa26 nc r26 t_d[10] f29 b_d[11] ac29 nc p27 t_d[11] f30 b_d[12] ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 90 zarlink semiconductor inc. ac28 nc p28 t_d[12] j26 b_d[13] e30 b_d[14] a23 b_a[12] e14 nc h26 b_d[15] b23 b_a[13] c15 nc e29 b_d[16] c23 b_a[14] b15 nc e26 b_d[17] e22 b_a[15] e13 nc d29 b_d[18] a22 b_a[16] a15 nc e28 b_d[19] b22 b_a[17] d14 nc g26 b_d[20] c22 b_a[18] c14 nc d30 b_d[21] e21 lb_a[20] d13 nc c30 b_d[22] d22 nc b14 nc e27 b_d[23] d20 nc a14 nc c29 b_clk e20 nc c13 nc d28 b_d[24] d21 nc e12 nc b30 b_d[25] a21 nc b13 nc f26 nc1 d19 nc a13 nc d26 nc2 b21 nc d12 nc a30 nc3 c21 nc c12 nc a29 nc4 a20 nc b12 nc b29 nc5 b20 nc a12 nc e25 agnd e19 nc c11 nc b28 dev_cfg[1] c20 nc e11 nc c28 avdd a19 nc b11 nc a28 b_d[26] b19 nc a11 nc a27 b_d[27] e18 nc e10 nc c27 b_d[28] c19 nc c10 nc d27 b_d[29] a18 nc b10 nc b27 b_d[30] d18 nc e9 nc e24 b_d[31] b18 nc a10 nc d25 b_adsc# c18 nc d11 nc b26 b_we# a17 nc d10 nc ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 91 zarlink semiconductor inc. a26 b_oe# e17 nc d8 nc a25 b_a[2] b17 nc d9 nc b25 b_a[3] c17 nc c9 nc c26 b_a[4] e16 nc b9 nc c25 b_a[5] d17 nc a9 nc e23 b_a[6] a16 s_clk c8 nc a24 b_a[7] b16 nc b8 nc b24 b_a[8] e15 nc a8 nc d23 b_a[9] c16 nc c7 nc d24 b_a[10] d16 nc e7 nc c24 b_a[11] d15 nc d7 nc b7 nc p15 vss ae7 vdd e8 nc p16 vss ae9 vdd a7 nc p17 vss f10 vdd d6 nc p18 vss f21 vdd c6 nc r13 vss f22 vdd e6 nc r14 vss f9 vdd b6 nc r15 vss g25 vdd a6 nc r16 vss g6 vdd a5 nc r17 vss j25 vdd b5 nc r18 vss j6 vdd c5 nc r25 vss k25 vdd b4 nc r6 vss k6 vdd d5 nc t13 vss ae12 vcc a4 nc t14 vss ae13 vcc a3 scan_en t15 vss ae14 vcc e5 agnd t16 vss ae17 vcc c4 nc6 t17 vss ae18 vcc b3 nc7 t18 vss ae19 vcc d4 nc8 t25 vss f12 vcc ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 92 zarlink semiconductor inc. a2 nc9 t6 vss f13 vcc ad6 vss u13 vss f14 vcc ae15 vss u14 vss f17 vcc ae16 vss u15 vss f18 vcc ae24 vss u16 vss f19 vcc ae25 vss u17 vss m25 vcc ae6 vss u18 vss m6 vcc f15 vss v13 vss n25 vcc f16 vss v14 vss n6 vcc f24 vss v15 vss p25 vcc f25 vss v16 vss p6 vcc f6 vss v17 vss u25 vcc f7 vss v18 vss u6 vcc n13 vss aa25 vdd v25 vcc n14 vss aa6 vdd v6 vcc n15 vss ab25 vdd w25 vcc n16 vss ab6 vdd w6 vcc n17 vss ad25 vdd n18 vss ae10 vdd p13 vss ae21 vdd p14 vss ae22 vdd ball no. signal name ball no. signal name ball no. signal name table 9 - ball signal name (continued)
MVTX2801 data sheet 93 zarlink semiconductor inc. 11.4 characteristics and timing 11.4.1 absolute maximum ratings storage temperature -65 o c to +150 o c operating temperature -40 o c to +85 o c maximum junction temperature +125 o c supply voltage vdd with resp ect to vss +3.0 v to +3.6 v supply voltage vdd with resp ect to vss +2.38 v to +2.75 v voltage on input pins -0.5 v to (vdd + 3.3 v) caution: stress above those listed may damage the devi ce. exposure to the absolute maximum ratings for extended periods may affect device reliability. functionality at or above these limits is not implied. 11.4.2 dc electrical characteristics vdd = 3.0 v to 3.6 v (3.3v +/- 10%) t ambient = -40 o c to +85 o c vdd = 2.5v +10% - 5%
MVTX2801 data sheet 94 zarlink semiconductor inc. 11.4.3 recommended operating conditions symbol parameter descri ption min type max unit fosc frequency of operation 133 mhz i cc supply current - @ 133 mhz (vdd = 3.3v) 680 850 ma i dd supply current - @ 133 mhz (vdd = 2.5v) 1300 1500 ma v oh output high voltage (cmos) 2.4 v v ol output low voltage (cmos) 0.4 v v ih-ttl input high voltage (ttl 5v tolerant) 2.0 vdd + 2.0 v v il-ttl input low voltage (ttl 5v tolerant) 0.8 v i il input leakage current (0.1 v < v in < vcc) 10 a i ol output leakage current (0.1 v < vout < vcc) 10 a c in input capacitance 5 pf c out output capacitance 5 pf c i/o i/o capacitance 7 pf ja thermal resistance with 0 air flow 11.2 c/w ja thermal resistance with 1 m/s air flow 9.9 c/w ja thermal resistance with 2 m/s air flow 8.7 c/w jc thermal resistance between junction and case 3.3 c/w table 10 - recommended operating conditions
MVTX2801 data sheet 95 zarlink semiconductor inc. 11.5 ac characteristics and timing 11.5.1 typical reset & bootstrap timing diagram figure 6 - typical reset & bootstrap timing diagram symbol parameter min typ note: r1 delay until resout# is tri-stated 10ns resout# state is then determined by the external pull-up/down resistor r2 bootstrap stabilization 1 s10 s bootstrap pins sampled on rising edge of s_rst# 1 1. the t_d[15:0] pins will switch over to the led inte rface functionality in 3 sclk cycles after s_rst# goes high r3 resout# assertion 2ms table 11 - reset & bootstrap timing resout# tri-stated s_rst# r1 r2 r3 bootstrap pins inputs outputs outputs
MVTX2801 data sheet 96 zarlink semiconductor inc. 11.5.2 local frame buffer zbt sram memory interface 11.5.2.1 local zbt sram memory interface a figure 7 - local memory interface - input setup and hold timing figure 8 - local memory interface - output valid delay timing symbol parameter (sclk= 133mhz) min (ns) max (ns) note: l1 la_d[63:0] input set-up time 2.5 l2 la_d[63:0] input hold time 1 l3 la_d[63:0] output valid delay 3 5 c l = 25pf l4 la_a[20:3] output valid delay 3 5 c l = 30pf l6 la_cs[1:0]# output valid delay 3 5 c l = 30pf l9 la_we# output valid delay 3 5 c l = 25pf table 12 - ac characteristics - local frame buffer zbt-sram memory interface a l1 l2 la_clk la_d[63:0] l3-min l3-max l4-min l4-max l6-min l6-max l9-min l9-max la_clk la_d[63:0] la_a[20:3] la_cs[1,0]# la_rw#
MVTX2801 data sheet 97 zarlink semiconductor inc. 11.5.3 local switch database sbram memory interface 11.5.3.1 local sbram memory interface figure 9 - local memory interface - input setup and hold timing figure 10 - local memory interface - output valid delay timing (sclk= 133mhz) symbol parameter min (ns) max (ns) note: l1 b_d[31:0] input set-up time 2.5 l2 b_d[31:0] input hold time 1 l3 b_d[31:0] output valid delay 3 5 c l = 25pf l4 b_a[18:2] output valid delay 3 5 c l = 30pf l6 b_adsc# output valid delay 3 5 c l = 30pf l10 b_we# output valid delay 3 5 c l = 25pf l11 b_oe# output valid delay 3 4 c l = 25pf table 13 - ac characteristics - local switch database sbram memory interface l1 l2 b_clk b_d[31:0] l3-min l3-max l4-min l4-max l6-min l6-max l10-min l10-max l11-min l11-max b_clk b_d[31:0] b_a[18:2] b_adsc# b_we# b_oe#
MVTX2801 data sheet 98 zarlink semiconductor inc. 11.5.4 media independent interface figure 11 - ac characteristics - media independent interface figure 12 - ac characteristics - media independent interface (mii_txclk & g_rxclk = 25mhz) symbol parameter min (ns) max (ns) note: m2 g[3:0]_rxd[3:0] input setup time 4 m3 g[3:0]_rxd[3:0] input hold time 1 m4 g[3:0]_crs_dv input setup time 4 m5 g[3:0]_crs_dv input hold time 1 m6 g[3:0]_txen outp ut delay time 3 11 c l = 20 pf m7 g[3:0]_txd[3:0] output delay time 3 11 c l = 20 pf table 14 - ac characteristics - media independent interface m6-min m6-max m7-min m7-max mii_txclk[3:0] g[3:0]_txen g[3:0] _txd[3:0] m2 g[3:0]_rxclk g[3:0]_rxd[3:0] g[3:0]_crs_dv m3 m4 m5
MVTX2801 data sheet 99 zarlink semiconductor inc. 11.5.5 gigabit media independent interface figure 13 - ac characteristics- gmii figure 14 - ac characteristics - gigabit media independent interface (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g1 g[3:0]_rxd[7:0] input setup times 2 g2 g[3:0]_rxd[7:0] input hold times 1 g3 g[3:0]_rx_dv input setup times 2 g4 g[3:0]_rx_dv input hold times 1 g5 g[3:0]_rx_er input setup times 2 g6 g[3:0]_rx_er input hold times 1 g7 g[3:0]_crs input setup times 2 table 15 - ac characteristics - gigabit media independent interface g12-min g12-max g13-min g13-max g14-min g14-max g[3:0]_txclk g[3:0]_txd[7:0] g[3:0]_tx_en g[3:0]_tx_er g[3:0]_rxclk g1 g2 g[3:0]_rxd[7:0] g3 g4 g[3:0]_rx_dv g5 g6 g[3:0]_rx_er g7 g8 g [ 3:0 ]_ rx _ crs
MVTX2801 data sheet 100 zarlink semiconductor inc. 11.5.6 pcs interface figure 15 - ac characteristics - pcs interface figure 16 - ac characteristics - pcs interface g8 g[3:0]_crs inpu t hold times 1 g12 g[3:0]_txd[7:0] ou tput delay times 1 5 c l = 20pf g13 g[3:0]_tx_en output delay times 1 5 c l = 20pf g14 g[3:0]_tx_er output delay times 1 5 c l = 20pf (g_rclk & g_refclk = 125mhz) symbol parameter min (ns) max (ns) note: g21 g[3:0]_rxd[9:0] input setup times ref to g_rxclk 2 g22 g[3:0]_rxd[9:0] input hold times ref to g_rxclk 1 g23 g[3:0]_rxd[9:0] input setup times ref to g_rxclk1 2 table 16 - ac characteristics - pcs interface (g_rclk & g_refclk = 125mhz) table 15 - ac characteristics - gigabit media independent interface (continued) g30-min g30-max g[3:0]_txclk g[3:0]_txd[9:0] g[3:0]_rxclk1 g[3:0]_rxclk g[3:0]_rxd[9:0] g[3:0]_rx_crs
MVTX2801 data sheet 101 zarlink semiconductor inc. 11.5.7 led interface figure 17 - ac characteristics - led interface g24 g[3:0]_rxd[9:0] input hold times ref to g_rxclk1 1 g25 g[3:0]_crs input setup times 2 g26 g[3:0]_crs input hold times 1 g30 g[3:0]_txd[9:0] output delay times 1 5 c l = 20pf variable freq. symbol parameter min (ns) max (ns) note: le5 led_syn output valid delay 1 7 c l = 30pf le6 led_bit output valid delay 1 7 c l = 30pf table 17 - ac characteristics - led interface (g_rclk & g_refclk = 125mhz) table 16 - ac characteristics - pcs interface le5-min le5-max le6-min le6-max led_clk led_syn led_bit
MVTX2801 data sheet 102 zarlink semiconductor inc. 11.5.8 mdio input setup and hold timing figure 18 - mdio input setup and hold timing figure 19 - mdio output delay timing 1mhz symbol parameter min (ns) max (ns) note: d1 mdio input setup time 10 d2 mdio input hold time 2 d3 mdio output delay time 1 20 c l = 50pf table 18 - mdio timing mdc d1 d2 mdio d3-min d3-max mdc mdio
MVTX2801 data sheet 103 zarlink semiconductor inc. 11.5.9 i 2 c input setup timing figure 20 - i 2 c input setup timing figure 21 - i 2 c output delay timing 11.5.10 serial interface setup timing figure 22 - serial interface setup timing figure 23 - serial interface output delay timing 500khz symbol parameter min (ns) max (ns) note: s1 sda input setup time 20 s2 sda input hold time 1 s3 sda output delay time 1 20 cl = 30pf open drain output. low to high transistor is controlled by external pullup resistor. table 19 - i 2 c timing scl s1 s2 sda s3-min s3-max scl sda strobe d1 d2 ps_di d1 d2 d4 d5 d3-min d3-max strobe ps_do
MVTX2801 data sheet 104 zarlink semiconductor inc. table 20 - serial interface timing (sclk =133 mhz) symbol parameter min (ns) max (ns) note: d1 ps_di setup time 20 d2 ps_di hold time 10 d3 ps_do output delay time 1 50 c l = 100pf d4 strobe low time 5 s d5 strobe high time 5 s
apprd. issue date acn package code previous package codes: conforms to jedec ms - 034 e b e e1 a2 d d1 a a1 40.20 39.80 34.50 ref 596 1.27 0.60 0.90 34.50 ref 1.17 ref 39.80 min 0.50 2.20 40.20 2.46 0.70 max 6. substrate thickness is 0.56 mm 4. n is the number of solder balls 2. dimension "b" is measured at the maximum solder ball diameter 1. controlling dimensions are in mm 5. not to scale. note: d e e1 d1 e a a1 a2 b 3. seating plane is defined by the spherical crowns of the solder balls.
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